verilog写流水灯

 

代码如下：

module first_led(
	input clk,rst,
	output wire out_clk,
	output reg [7:0]oled
);
reg [24:0]count;
parameter data =25'd2000000;
assign out_clk = clk;
always @(posedge clk or negedge rst)
begin 
		if(!rst)
			begin 
				oled <= 8'b0000_0001;
				count <= 0;
			end
		else    
			begin 
				count <= count+1'b1;
				if(count==data)
					begin 					
							count <=0;						
							oled <=oled==8'b1000_0000 ? 8'b0000_0001:oled<<1'b1;
					end
				
			end
end
endmodule