序列检测器(检测"10010序列")

最新推荐文章于 2025-07-06 12:41:57 发布

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最新推荐文章于 2025-07-06 12:41:57 发布 · 3w 阅读

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#FPGA

在这里插入图片描述
IDLE为初始状态，A代表第一个状态"1"，B代表第二个状态"10",C代表第三个状态"100",D代表第四个状态"1001",E代表要输出的状态"10010"，G和F代表多余的状态分别为"1000"和"10001"。

module cy4( clk,rst_b,In,Y);
input clk,rst_b,In;
output Y;
reg[2:0]current_state,next_state;
wire Y;
parameter IDLE = 3'd0,//每个十进制数代表不同的状态
             A = 3'd1,
			 B = 3'd2,
			 C = 3'd3,
			 D = 3'd4,
			 E = 3'd5,//输出为1的状态
			 F = 3'd6,
			 G = 3'd7;
assign Y = (next_state == D && In == 0)?1:0;
//状态为D时又收到了0，表明10010收到应有输出Y为高
always @(posedge clk or negedge rst_b)
if(!rst_b) current_state <= IDLE;
else current_state <= next_state;

always @(In,current_state)
case(current_state)
IDLE: if(In == 1) next_state <= A;
      else next_state <= IDLE;
A: if(In == 0) next_state <= B;
   else next_state <= A;
B: if(In == 0) next_state <= C;
   else next_state <= F;
C: if(In == 1) next_state <= D;
   else next_state <= G;
D: