<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[qq_41946913的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/qq_41946913</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; qq_41946913]]></copyright><item><title><![CDATA[【SystemVerilog 2023 Std】第6章 数据类型 Data types (5)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/149022057</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/149022057</guid><author>qq_41946913</author><pubDate>Wed, 16 Jul 2025 14:00:00 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准。]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第6章 数据类型 Data types (4)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/149002973</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/149002973</guid><author>qq_41946913</author><pubDate>Wed, 09 Jul 2025 12:00:00 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准。]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第6章 数据类型 Data types (3)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148781361</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148781361</guid><author>qq_41946913</author><pubDate>Wed, 02 Jul 2025 11:30:00 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准。]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第6章 数据类型 Data types (2)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148731715</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148731715</guid><author>qq_41946913</author><pubDate>Sun, 29 Jun 2025 21:06:15 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准。]]></description><category></category></item><item><title><![CDATA[Perl语言基础]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/138139490</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/138139490</guid><author>qq_41946913</author><pubDate>Mon, 23 Jun 2025 13:13:14 +0800</pubDate><description><![CDATA[Perl（Practical Extraction and Report Language）查看版本信息：
第一行是Perl的路径，根据实际情况修改,通过命令来确认路径
2. 数据类型
创建一个变量时，会在内存中保留一些空间标量是一个数据单元，该数据可能是整数、浮点数、字符、字符串
2.1.1 数值标量

2.1.2 字符标量

2.1.3 标量操作

2.1.4 多行字符串
想在程序中引入多行字符串，使用单引号
2.1.5 特殊标量
,,代表程序中那个点的当前文件名、行号和包号
2.2 数组
数组是存储标]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第6章 数据类型 Data types (1)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148682162</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148682162</guid><author>qq_41946913</author><pubDate>Sat, 21 Jun 2025 21:22:53 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准。]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第5章 词法约定 Lexical conventions (2)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148631028</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148631028</guid><author>qq_41946913</author><pubDate>Fri, 13 Jun 2025 17:11:23 +0800</pubDate><description><![CDATA[时间值（Time）应采用整数或定点格式书写，并紧随其后（不带空格）加上时间单位（、、、、、）。
时间字面量被解释为按当前时间单位缩放后的 realtime 值。字符串字面量（string literal）是由一对双引号（）括起来的字符序列，称为带引号的字符串；或者由三对双引号（）括起来的字符序列，称为三重引号字符串。字符串字面量的长度没有预定义限制。
语法如下：
在字符串字面量中，不可打印字符和其他特殊字符可通过字符串转义序列表示，详见 5.9.1 节。对未转义的不可打印 ASCII 字符的支持取决于具体实]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第5章 词法约定 Lexical conventions (1)]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148625045</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148625045</guid><author>qq_41946913</author><pubDate>Fri, 13 Jun 2025 17:10:17 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准《IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language》]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第4章 调度语义 Scheduling semantics]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148562817</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148562817</guid><author>qq_41946913</author><pubDate>Thu, 12 Jun 2025 15:35:32 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准《IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language》]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第3章 设计和验证构建块 Design and verification building blocks]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148536886</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148536886</guid><author>qq_41946913</author><pubDate>Tue, 10 Jun 2025 16:02:28 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准《IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language》]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】第2章 参考标准 Normative references]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148534142</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148534142</guid><author>qq_41946913</author><pubDate>Mon, 09 Jun 2025 14:34:18 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准《IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language》本标准的应用不可缺少以下参考文献。对于注明日期的参考文献，只适用所引用的版本；对于未注日期的参考文献，则适用其最新版本。]]></description><category></category></item><item><title><![CDATA[【SystemVerilog 2023 Std】 第1章 综述 Overview]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/148479368</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/148479368</guid><author>qq_41946913</author><pubDate>Mon, 09 Jun 2025 13:48:54 +0800</pubDate><description><![CDATA[参考资料：IEEE Std 1800-2023标准《IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language》]]></description><category></category></item><item><title><![CDATA[SystemVerilog Assertion断言]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/134815540</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/134815540</guid><author>qq_41946913</author><pubDate>Sat, 27 Apr 2024 09:22:10 +0800</pubDate><description><![CDATA[参考书目：《SystemVerilog Assertion应用指南》、RKV课程。]]></description><category></category></item><item><title><![CDATA[Python基础语法合集（极简）]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/138183830</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/138183830</guid><author>qq_41946913</author><pubDate>Fri, 26 Apr 2024 22:07:15 +0800</pubDate><description><![CDATA[在Python中，可以为实例属性和方法设置私有权限，即设置某个实例属性或实例方法不继承给子类。私有属性和私有变量只能在类里面访问和修改self.kongfu = '[古法煎饼果⼦配方]'print(f'运⽤{self.kongfu}制作煎饼果子')self.kongfu = '[⿊马煎饼果子配方]'print(f'运⽤{self.kongfu}制作煎饼果子')self.kongfu = '[独创煎饼果子配方]'#定义私有属性#定义私有方法。]]></description><category></category></item><item><title><![CDATA[AHB协议]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/135395541</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/135395541</guid><author>qq_41946913</author><pubDate>Fri, 05 Jan 2024 10:25:28 +0800</pubDate><description><![CDATA[Decoder作用：确定HADDR传输去哪，   Decoder处理HADDR的高位，根据高位的不同来决定HSEL，具体取几位取决于Slave的地址范围（假设Slave1有16bit地址，则HADDR的高16bit给Decoder，当某种情况下选中HSEL1，HADDR的低16bit给Slave）；Slave之间的地址范围要错开，不能重叠。]]></description><category></category></item><item><title><![CDATA[APB协议]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/135391344</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/135391344</guid><author>qq_41946913</author><pubDate>Thu, 04 Jan 2024 20:07:51 +0800</pubDate><description><![CDATA[Advanced Peripheral Bus(APB, 先进外设总线）低功耗，接口简单，非流水线每次传输至少两个周期主要用于低速、功耗低的外围。]]></description><category></category></item><item><title><![CDATA[UVM入门-组件]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/134071725</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/134071725</guid><author>qq_41946913</author><pubDate>Fri, 27 Oct 2023 20:31:18 +0800</pubDate><description><![CDATA[对于更复杂的检查要求，可将数据发送至其他验证组件，例如scoreboard、reference model或coverage collector。从uvm_sequencer中获取事务（transaction），经转化在接口中对DUT进行时序激励。uvm_agent作为一个标准单元，在更上层的继承中应该被例化到uvm_env。uvm_env在更高的复用中，可以被其他uvm_env所嵌套。在总线协议或内部信号协议观察时，可以做一些功能和时序的检查。未扩展新的函数,扩展用来通信的端口和变量。]]></description><category></category></item><item><title><![CDATA[UVM入门-核心基类、phase机制、config机制、消息管理]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/133976793</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/133976793</guid><author>qq_41946913</author><pubDate>Mon, 23 Oct 2023 16:11:03 +0800</pubDate><description><![CDATA[第一个和第二个参数组合起来组成路径（uvm_component实例的指针+相对此实例的路径），第三个参数是传给目标中的哪个成员，第四个参数是设置的变量。，意思就是说：拷贝出来的目标对象的指针和源对象的指针指向的内存空间是同一块空间，浅拷贝只是一种简单的拷贝，让几个对象公用一个内存。将UVM仿真阶段层次化（各个phase的先后执行顺序，处于同一phase中的层次化组件之间的phase的先后关系）通常情况下，消息处理的方式是同消息的严重级别对应的。：低于过滤的开关，该消息会打印出来，否则不会被打印。]]></description><category></category></item><item><title><![CDATA[UVM入门-factory]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/133965445</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/133965445</guid><author>qq_41946913</author><pubDate>Sun, 22 Oct 2023 15:53:50 +0800</pubDate><description><![CDATA[验证环境的动产，包含generator、stimulator、monitor、agent、checker/reference model、environment、test等组件在uvm_component的子类中均有对应的组件。UVM验证环境的构成：1.构成环境的层次：用过uvm_component类完成；2.构成环境的属性和数据传输：通过uvm_object类完成。更方便地替换验证环境中的实例或注册了的类型（在UVM中称作覆盖，override），带来了配置的灵活性。对验证环境的共同需求。]]></description><category></category></item><item><title><![CDATA[SV语言-高级话题]]></title><link>https://blog.youkuaiyun.com/qq_41946913/article/details/133935665</link><guid>https://blog.youkuaiyun.com/qq_41946913/article/details/133935665</guid><author>qq_41946913</author><pubDate>Fri, 20 Oct 2023 14:38:31 +0800</pubDate><description><![CDATA[显示转换：需要操作符号或系统函数介入，如静态转换和动态转换隐式转换：不需要进行转换的操作：tgt '(src)，  不会对转换值做检查类句柄向下转换，即父类句柄转换为子类句柄时，需要$cast()子类句柄赋给父类时，编译器认为合法，但子类句柄和父类句柄调用相同对象时，可能有不同表现$ cast(tgt,src)会检查句柄所指向的对象类型，一旦元对象跟目的句柄是同一类型，或者目的句柄的扩展类，$cast(）执行成功返回1，否则返回0。]]></description><category></category></item></channel></rss>