VHDL元件例化

课设又要用到VHDL了，自学了一下元件例化，还是比较简单的
正文开始

一、写好需要用到的元件
这里我用一个简单的12进制计数器和7段数码管显示程序

-------------------------12进制计数器-------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT12 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC );
END CNT12;
ARCHITECTURE behav OF CNT12 IS
BEGIN
PROCESS(CLK, RST, EN)
VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	IF RST = '1' THEN CQI := (OTHERS =>'0') ; --计数器异步复位
	ELSIF CLK'EVENT AND CLK='1' THEN --检测时钟上升沿
		IF EN = '1' THEN --检测是否允许计数（同步使能）
			IF CQI < 11 THEN CQI := CQI + 1; --允许计数, 检测是否小于11
			ELSE CQI := (OTHERS =>'0'); --大于11，计数值清零
			END IF;
		END IF;
	END IF;
	IF CQI = 11 THEN COUT <= '1'; --计数大于11，输出进位信号
	ELSE COUT <= '0';
	END IF;
	CQ <= CQI; --将计数值向端口输出
END PROCESS;
END behav;

--------------------------------------7段数码管显示-----------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY DECL7S IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
END ;
ARCHITECTURE one OF DECL7S IS
BEGIN
PROCESS( A )
BEGIN
CASE A IS
WHEN "0000" => LED7S <= "0111111" ;--0
WHEN "0001" => LED7S <= "0000110" ;--1
WHEN "0010" => LED7S <= "1011011" ;--2
WHEN "0011" => LED7S <= "1001111" ;--3
WHEN "0100" => LED7S <= "1100110" ;--4
WHEN "0101" => LED7S <= "1101101" ;--5
WHEN "0110" => LED7S <= "1111101" ;--6
WHEN "0111" => LED7S <= "0000111" ;--7
WHEN "1000" => LED7S <= "1111111" ;--8
WHEN "1001" => LED7S <= "1101111" ;--9
WHEN "1010" => LED7S <= "1110111" ;--10
WHEN "1011" => LED7S <= "1111100" ;--11
WHEN "1100" => LED7S <= "0111001" ;--12
WHEN "1101" => LED7S <= "1011110" ;--13
WHEN "1110" => LED7S <= "1111001" ;--14
WHEN "1111" => LED7S <= "1110001" ;--15
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END ;

二、以上两个元件都准备好了以后，写顶层文件

------------------------------top.vhd-------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIYAN_3 IS
PORT ( 
	CLK_T,RST_T,EN_T: IN STD_LOGIC;
	COUT_T: OUT STD_LOGIC;
	LED7S_T: OUT STD_LOGIC_VECTOR(6 downto 0)
) ;
END SHIYAN_3;
ARCHITECTURE one OF SHIYAN_3 IS

component CNT12
port(CLK,RST,EN : IN STD_LOGIC;
		CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		COUT : OUT STD_LOGIC);
end component CNT12;
component DECL7S
port( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
end component DECL7S;

signal CQ_T:std_LOGIC_VECTOR(3 downto 0);
BEGIN
	U1:CNT12
	port map(CLK_T,RST_T,EN_T,CQ_T,COUT_T);
	U2:DECL7S
	PORT MAP(CQ_T,LED7S_T);
END ;

其中
component CNT12
port(CLK,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC);
end component CNT12;
component DECL7S
port( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
end component DECL7S;

是申明元件。

后面的port map是将元件的端口与顶层的信号或者端口对应起来。

最重要的一点就是：将top.vhd 设置为顶层。

需要完整工程文件可以在此下载