modelsim仿真ISE工程时出现# ** Error: (vlog-19) Failed to access library 'rtl_work' at "rtl_work

本文解决了一个常见的问题:在使用ISE调用Modelsim进行仿真时,若先前已使用Modelsim仿真过Quartus II工程,再次仿真ISE工程会遇到错误。解决方案为在Modelsim中删除work(unavailable)libraryrtl_work,即可正常进行ISE工程的仿真。

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今天在使用ISE调用Modelsim的时候,遇到下面图1的错误:

  

图1 Modelsim出现的错误

  找了半天解决方法,找到了下面的解答(http://blog.sina.com.cn/s/blog_6e394a3d0101722o.html)。

  通常情况下一台电脑上即装有ISE,又装有quartus ii且二者的仿真库都在modelsim里编译好,在用modelsim仿真过quartus ii工程之后再用modelsim仿真ISE工程就会出现如题所示错误:Error: (vlog-19) Failed to access library 'rtl_work' at "rtl_work",此时在modelsim界面的library栏处找到work(unavailable) library rtl_work,将其删除,即可进行ISE工程的仿真。

    以后每次仿真过quartus ii工程之后再仿真ISE工程可能都会出现这种情况,那就每次都记得出现错误时就把work(unavailable) library rtl_work删除,再进行ISE工程的仿真。

删除了work(unavailable) library rtl_work之后,在仿真就没有错误了!

 

上面是博客:modelsim仿真ISE工程时出现# ** Error: (vlog-19) Failed to access library 'rtl_work' at "rtl_work

的内容。

我的错误也类似,只要将library后面跟着的目录在modelsim删掉在运行就行了。

我的是提示这个work有问题

然后我先将Modelsim下面的那个work先删了,然后在点击运行xilinx的仿真文件.fdo文件。

就能成功运行了。

WINDOW2 START Reading C:/questasim64_10.7c/tcl/vsim/pref.tcl # 10.7c # do ../TB/run2.do # ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 10.7c Lib Mapping Utility 2018.08 Aug 18 2018 # vmap work work # Modifying modelsim.ini # QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 # Start time: 15:42:27 on Mar 14,2025 # vlog "+cover=bsfce" ../RTL/DIG_clk_cnt.v # -- Compiling module DIG_clk_cnt # # Top level modules: # DIG_clk_cnt # End time: 15:42:27 on Mar 14,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 # Start time: 15:42:27 on Mar 14,2025 # vlog "+cover=bsfce" ../RTL/Dynamic_dispaly.v # -- Compiling module Dynamic_dispaly # # Top level modules: # Dynamic_dispaly # End time: 15:42:27 on Mar 14,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 # Start time: 15:42:27 on Mar 14,2025 # vlog "+cover=bsfce" ../RTL/top.v # -- Compiling module top # # Top level modules: # top # End time: 15:42:27 on Mar 14,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # case004 # ../Output/func_report/Log/case004.log # ../Output/func_report/Wlf/case004.wlf # ../Output/func_report/Ucdb/case004.ucdb # QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 # Start time: 15:42:27 on Mar 14,2025 # vlog ../TB/testbench.v # -- Compiling module testbench # # Top level modules: # testbench # End time: 15:42:27 on Mar 14,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -voptargs="+acc" -coverage work.testbench -l ../Output/func_report/Log/case004.log # Start time: 15:42:27 on Mar 14,2025 # ** Note: (vsim-8009) Loading existing optimized design _opt # // Questa Sim-64 # // Version 10.7c win64 Aug 18 2018 # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading work.testbench(fast) # Loading work.top(fast) # Loading work.DIG_clk_cnt(fast) # Loading work.Dynamic_dispaly(fast) # rst_n is 1 # ** Note: $stop : C:/sim_env/sim/VSIM/../TB/testbench.v(20) # Time: 20 ns Iteration: 1 Instance: /testbench # Break in Module testbench at C:/sim_env/sim/VSIM/../TB/testbench.v line 20 # Stopped at C:/sim_env/sim/VSIM/../TB/testbench.v line 20 # Dataset "sim" exported as WLF file: ../Output/func_report/Wlf/case004.wlf. # ** Error: couldn't read file "../TB/error_detection.tcl": no such file or directory # Error in macro ./../case/case004/main.tcl line 19 # couldn't read file "../TB/error_detection.tcl": no such file or directory # while executing # "source ../TB/error_detection.tcl"
03-15
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