失败的状态机与led灯&&修改

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:50:08 09/04/2018 
// Design Name: 
// Module Name:    ledstate 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
//module ledstate(
//input clk,
//input rst,
//input switch,
//output reg[7:0] led
//);
//
//reg start;
//reg[3:0] cnt;
//always@(posedge clk or negedge rst)
//if(!rst) cnt <= 4'd0;
//else if(cnt == 4'hf) 
//begin start <= 1'b1;
//      cnt <= 4'd0;
//      end
//else begin cnt <= cnt+1'b1;
//           start <= 1'b0;
//      end
//
//reg[2:0] cstate,nstate;
//parameter idle = 3'b000;
//parameter second = 3'b001;
//parameter third = 3'b010;
//parameter four = 3'b011;
//parameter five = 3'b100;
//
////逻辑的变化
//always@(start or rst)
//if(!rst) cstate <= idle;
//else begin
//case(cstate)
//idle:if(!switch && start) nstate <= second;
//     else nstate <= idle;
//second:if(start) nstate <= third;
//     else nstate <= second;
//third:if(start) nstate <= four;
//else nstate <= third;
//four:if(start) nstate <= five;
//else nstate <= four;
//five: nstate <= idle;
//default nstate <= idle;
//endcase
//end
//
////状态对应的行为
//always@(start or rst)
//if(!rst) 
//begin cstate <= idle;
//end
//else begin
//case(nstate) 
//idle:led <= 8'b00000000;
//second:led <= 8'b00110011;
//third:led <= 8'b11001100;
//four:led <= 8'b10101010;
//five:led <= 8'b00000000;
//endcase
//end
//
//wire [35:0] CONTROL;
//wire [15:0] TRIG0;
//ledstate_icon stateicon (
//    .CONTROL0(CONTROL) // INOUT BUS [35:0]
//);
//ledstate_ila stateila (
//    .CONTROL(CONTROL), // INOUT BUS [35:0]
//    .CLK(clk), // IN
//    .TRIG0(TRIG0) // IN BUS [15:0]
//);
//
//assign TRIG0[15:12] = cnt;
//assign TRIG0[11] = start;
//assign TRIG0[10] = switch;
//assign TRIG0[9] = led[7];
//assign TRIG0[8] = led[6];
//assign TRIG0[7] = led[5];
//assign TRIG0[6] = led[4];
//assign TRIG0[5] = led[3];
//assign TRIG0[4] = led[2];
//assign TRIG0[3] = led[1];
//assign TRIG0[2] = led[0];
//assign TRIG0[1] = rst;
//assign TRIG0[0] = clk;
//
//endmodule
//

这个程序的语法及综合没有问题，但是状态机却没有按照理想的往下跑，要进一步修改，再充充电

经过一天的资料搜索与修改，最终写出了还存在小问题的程序，问题是led灯的转变过程存在不明状态

module ledstate(
input clk,
input rst,
input switch,
output reg[7:0] led
);

reg start;
reg[23:0] cnt;
always@(posedge clk or negedge rst)
if(!rst) cnt <= 24'd0;
else if(cnt == 24'hffffff) 
begin start <= ~start;
      cnt <= 24'd0;
      end
else cnt <= cnt+1'b1;

reg[3:0] cstate;
parameter idle = 4'b0000;
parameter second = 4'b0001;
parameter third = 4'b0010;
parameter four = 4'b0100;
parameter five = 4'b1000;

//逻辑的变化
always@(posedge clk or negedge rst)
if(!rst) cstate <= idle;
else begin
case(cstate)
idle:if(start) begin 
led <= 8'b11111111;
cstate <= second;
end
else cstate <= idle;

second:if(start) begin
led <= 8'b11110011;
cstate <= third;
end
else cstate <= second;

third:if(start) begin
led <= 8'b10110011; 
cstate <= four;
end
else cstate <= third;

four:if(start) begin
led <= 8'b10101010;
cstate <= five;
end
else cstate <= four;

five:if(start) begin
led <= 8'b00000000;
cstate <= idle;
end
else cstate <= five;

default cstate <= idle;
endcase
end

wire [35:0] CONTROL;
wire [15:0] TRIG0;
ledstate_icon stateicon (
    .CONTROL0(CONTROL) // INOUT BUS [35:0]
);
ledstate_ila stateila (
    .CONTROL(CONTROL), // INOUT BUS [35:0]
    .CLK(clk), // IN
    .TRIG0(TRIG0) // IN BUS [15:0]
);

assign TRIG0[11] = start;
assign TRIG0[10] = switch;
assign TRIG0[9] = led[7];
assign TRIG0[8] = led[6];
assign TRIG0[7] = led[5];
assign TRIG0[6] = led[4];
assign TRIG0[5] = led[3];
assign TRIG0[4] = led[2];
assign TRIG0[3] = led[1];
assign TRIG0[2] = led[0];
assign TRIG0[1] = rst;
assign TRIG0[0] = clk;

endmodule