SystemVerilog 接口之采样竞争
看一下race代码
`timescale 1ns/1ns
module race1;
bit clk1, clk2;
bit rstn;
logic[7:0] d1;
initial begin
forever #5 clk1 <= !clk1; //5ns一翻转,所以时钟周期是10ns
end
always @(clk1) clk2 <= clk1; //当clk1上升沿到来时,赋值给clk2,利用组合逻辑使得clk2跟着clk1一起跳转
initial begin
#10
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2022-02-13 10:58:27 ·
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