xref: /MT6769_15.0.0_release/vnd/vendor/mediatek/proprietary/bootable/bootloader/lk/platform/mt6768/gpio_init.c
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1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein is
5 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
6 * the prior written permission of MediaTek inc. and/or its licensors, any
7 * reproduction, modification, use or disclosure of MediaTek Software, and
8 * information contained herein, in whole or in part, shall be strictly
9 * prohibited.
10 *
11 * MediaTek Inc. (C) 2017. All rights reserved.
12 *
13 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
14 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
15 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
16 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
17 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
19 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
20 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
21 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
22 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
23 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
24 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
25 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
26 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
27 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
28 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
29 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
30 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
31 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
32 *
33 * The following software/firmware and/or related documentation ("MediaTek
34 * Software") have been modified by MediaTek Inc. All revisions are subject to
35 * any receiver's applicable license agreements with MediaTek Inc.
36 */
37 #include <platform/mt_gpio.h>
38
39 #if !defined(FPGA_PLATFORM) && !defined(USE_DTB_NO_DWS)
40 #include <cust_power.h>
41 #include <cust_gpio_boot.h>
42 #endif
43
44 #include <platform/mt_reg_base.h>
45
46 #include <debug.h>
47 #define GPIO_INIT_DEBUG
48 /*----------------------------------------------------------------------------*/
49 #define GPIOTAG "[GPIO] "
50 #define GPIODBG(fmt, arg...) dprintf(INFO, GPIOTAG "%s: " fmt, __FUNCTION__ ,##arg)
51 #define GPIOERR(fmt, arg...) dprintf(INFO, GPIOTAG "%s: " fmt, __FUNCTION__ ,##arg)
52 #define GPIOVER(fmt, arg...) dprintf(INFO, GPIOTAG "%s: " fmt, __FUNCTION__ ,##arg)
53
54 #define GPIO_WR32(addr, data) DRV_WriteReg32(addr,data)
55 #define GPIO_RD32(addr) DRV_Reg32(addr)
56
57 #define ADDR_BIT 0
58 #define VAL_BIT 1
59 #define MASK_BIT 2
60
61 //#define GPIO_SET_DEFAULT_DBG
62
63 /*----------------------------------------------------------------------------*/
64 #ifdef FPGA_PLATFORM
65 void mt_gpio_set_default(void)
66 {
67 return;
68 }
69 #else
70
71 #include <platform/gpio_init.h>
72
73 /* #ifdef OPLUS_FEATURE_CHG_BASIC */
74 /* oplus add for user build disable uart */
75 #include <platform.h>
76 #include <platform/boot_mode.h>
77 /* #endif */
78
79 /* #ifdef OPLUS_FEATURE_CHG_BASIC */
80 /* oplus add for user build disable uart */
81 #define UART_DT_NODE_RX_NAME "rxpin"
82 #define UART_DT_NODE_TX_NAME "txpin"
83 #define UART_DT_NODE_NAME_SOC "/serial@11002000"
84 /* #endif */
85 #ifdef USE_DTB_NO_DWS
86 #include <libfdt.h>
87 #include <lk_builtin_dtb.h>
88 extern void msdc_gpio_and_pad_init_by_id(int id);
89 #define ELEMENTS_PER_GPIO 7
90 #define GPIO_DT_NODE_NAME "/gpio@10005000"
91 #define GPIO_DT_NODE_PROP_NAME "gpio_init_default"
92 int mt_gpio_get_default_chip_from_dtb(void)
93 {
94 void *lk_drv_fdt = get_lk_overlayed_dtb();
95
96 if (lk_drv_fdt == NULL)
97 panic("lk driver fdt is NULL!\n");
98 int off = fdt_path_offset(lk_drv_fdt, GPIO_DT_NODE_NAME);
99 unsigned int *data;
100 int len = 0, pin, j;
101
102 dprintf(INFO, "[GPIO] Found " GPIO_DT_NODE_NAME "at offset %d\n", off);
103 if (off < 0) {
104 dprintf(CRITICAL, "[GPIO] Failed to find " GPIO_DT_NODE_NAME " in dtb\n");
105 return -1;
106 } else {
107 data = (unsigned int *)fdt_getprop(lk_drv_fdt, off, GPIO_DT_NODE_PROP_NAME, &len);
108 if (len <= 0 || !data) {
109 dprintf(CRITICAL, "[GPIO] Fail to found property " GPIO_DT_NODE_PROP_NAME "\n");
110 return -1;
111 }
112 dprintf(INFO, "[GPIO] Found perperty at 0x%08x, len %d\n", (unsigned int)data, len);
113 }
114
115 if ((len > 0) && ((len % ELEMENTS_PER_GPIO) == 0)) {
116 len /= (ELEMENTS_PER_GPIO * 4); //Per element use 4 bytes */
117 for (j = 0; j < len; j++) {
118 pin = fdt32_to_cpu(*data);
119
120 if (pin < 0 || pin >= MT_GPIO_BASE_MAX) {
121 data += 7;
122 continue;
123 }
124
125 data++;
126 gpio_array[pin].mode = (unsigned char) fdt32_to_cpu(*data);
127
128 data++;
129 gpio_array[pin].dir = (unsigned char) fdt32_to_cpu(*data);
130
131 data++;
132 gpio_array[pin].dataout = (unsigned char) fdt32_to_cpu(*data);
133
134 data++;
135 gpio_array[pin].pullen = (unsigned char) fdt32_to_cpu(*data);
136
137 data++;
138 gpio_array[pin].pull = (unsigned char) fdt32_to_cpu(*data);
139
140 data++;
141 gpio_array[pin].smt = (unsigned char) fdt32_to_cpu(*data);
142
143 data++;
144 }
145 }
146
147 return 0;
148 }
149 #endif
150
151 void mt_gpio_set_default_chip(void)
152 {
153 unsigned pin = 0;
154
155 /* #ifdef OPLUS_FEATURE_CHG_BASIC */
156 /* oplus add for user build disable uart */
157 void *lk_drv_fdt = NULL;
158 unsigned int *data_rx;
159 unsigned int *data_tx;
160 int pin_rx = -1;
161 int pin_tx = -1;
162 int off1, len1, len2;
163 /* #endif */
164
165 #ifdef USE_DTB_NO_DWS
166 /*
167 * Pins set as GPIO_INIT_NO_COVER,
168 * mode setting will not override in
169 * mt_gpio_get_default_chip_from_dtb()
170 */
171 /* Init pin mode as 0xFF */
172 for (pin = 0; pin < MT_GPIO_BASE_MAX; pin++)
173 gpio_array[pin].mode = 0xFF;
174
175 if (mt_gpio_get_default_chip_from_dtb() < 0)
176 return;
177
178 /* #ifdef OPLUS_FEATURE_CHG_BASIC */
179 /* oplus add for user build disable uart */
180 lk_drv_fdt = get_lk_overlayed_dtb();
181
182 off1 = fdt_path_offset(lk_drv_fdt, UART_DT_NODE_NAME_SOC);
183 data_rx = (unsigned int *)fdt_getprop(lk_drv_fdt, off1, UART_DT_NODE_RX_NAME, &len1);
184 data_tx = (unsigned int *)fdt_getprop(lk_drv_fdt, off1, UART_DT_NODE_TX_NAME, &len2);
185 if (data_rx != NULL && data_tx != NULL) {
186 pin_rx = fdt32_to_cpu(*data_rx);
187 pin_tx = fdt32_to_cpu(*data_tx);
188 dprintf(CRITICAL, "[GPIO] len1=%d, len2=%d, data_rx=%d, data_tx=%d\n", len1, len2, pin_rx, pin_tx);
189 }
190 /* #endif */
191 #endif
192
193 for (pin = 0; pin < MT_GPIO_BASE_MAX; pin++) {
194 /* Skip pins which is set as GPIO_INIT_NO_COVER */
195 if (gpio_array[pin].mode == 0xFF)
196 continue;
197
198 /* set GPIOx_MODE*/
199 mt_set_gpio_mode(0x80000000 + pin , gpio_array[pin].mode);
200
201 /* set GPIOx_DIR*/
202 if (gpio_array[pin].dir != 0xFF)
203 mt_set_gpio_dir(0x80000000 + pin, gpio_array[pin].dir);
204
205 /* set GPIOx_PULL*/
206 if (gpio_array[pin].pullen == 0)
207 gpio_array[pin].pull = GPIO_NO_PULL;
208 if (gpio_array[pin].pull != 0xFF)
209 mt_set_gpio_pull_select(0x80000000 + pin, gpio_array[pin].pull);
210
211 /* set GPIOx_PULLEN*/
212 if (gpio_array[pin].pullen != 0xFF)
213 mt_set_gpio_pull_enable(0x80000000 + pin , gpio_array[pin].pullen);
214
215 /* set GPIOx_DATAOUT*/
216 if (gpio_array[pin].dataout != 0xFF)
217 mt_set_gpio_out(0x80000000 + pin, gpio_array[pin].dataout);
218
219 /* set GPIO0_SMT */
220 if (gpio_array[pin].smt != 0xFF)
221 mt_set_gpio_smt(0x80000000 + pin, gpio_array[pin].smt);
222
223 #ifdef GPIO_SET_DEFAULT_DBG
224 dprintf(CRITICAL, "GPIO%d desired: %d %d %d %d %d %d\n",
225 pin,
226 gpio_array[pin].mode,
227 gpio_array[pin].dir,
228 gpio_array[pin].pull,
229 gpio_array[pin].pullen,
230 gpio_array[pin].dataout,
231 gpio_array[pin].smt);
232
233 /* set GPIOx_MODE*/
234 dprintf(CRITICAL, "GPIO%d modified: %d %d %d %d %d %d\n",
235 pin,
236 mt_get_gpio_mode(0x80000000 + pin),
237 mt_get_gpio_dir(0x80000000 + pin),
238 mt_get_gpio_pull_select(0x80000000 + pin),
239 mt_get_gpio_pull_enable(0x80000000 + pin),
240 mt_get_gpio_out(0x80000000 + pin),
241 mt_get_gpio_smt(0x80000000 + pin));
242 #endif
243
244 }
245 /* #ifdef OPLUS_FEATURE_CHG_BASIC */
246 /* oplus add for user build disable uart */
247 #ifdef USER_LOAD
248 if (pin_rx == -1 || pin_tx == -1) {
249 dprintf(CRITICAL, "user build, but cannot read rx or tx pin!\n");
250 } else {
251 if (g_boot_mode == FACTORY_BOOT) {
252 dprintf(CRITICAL, "user build, but FTM mode, do nothing!\n");
253 } else if (g_boot_arg->log_dynamic_switch == 1) {
254 dprintf(CRITICAL, "user build, but oplus uart, do nothing!\n");
255 } else {
256 mt_set_gpio_mode(pin_rx, 0);
257 mt_set_gpio_pull_enable(pin_rx, 0);
258 mt_set_gpio_dir(pin_rx, 0);
259
260 mt_set_gpio_mode(pin_tx, 0);
261 mt_set_gpio_pull_enable(pin_tx, 0);
262 mt_set_gpio_dir(pin_tx, 0);
263
264 dprintf(CRITICAL, "user build, oplus set uart0 input & pulldown!\n");
265 }
266 }
267 #endif
268 /* #endif *//* OPLUS_FEATURE_CHG_BASIC */
269 }
270
271 void mt_gpio_set_default(void)
272 {
273 mt_gpio_set_default_chip();
274
275 return;
276 }
277 /*----------------------------------------------------------------------------*/
278 #if CHECK_POINT_TEST
279 #if defined(GPIO_INIT_DEBUG)
280 static GPIO_REGS saved;
281 #endif
282
283 void mt_gpio_checkpoint_save(void)
284 {
285 #if defined(GPIO_INIT_DEBUG)
286 GPIO_REGS *pReg = (GPIO_REGS*)(GPIO_BASE);
287 GPIO_REGS *cur = &saved;
288 int idx;
289
290 memset(cur, 0x00, sizeof(*cur));
291 for (idx = 0; idx < sizeof(pReg->dir)/sizeof(pReg->dir[0]); idx++)
292 cur->dir[idx].val = GPIO_RD32(&pReg->dir[idx]);
293 #if 0
294 for (idx = 0; idx < sizeof(pReg->pullen)/sizeof(pReg->pullen[0]); idx++)
295 cur->pullen[idx].val = GPIO_RD32(&pReg->pullen[idx]);
296 for (idx = 0; idx < sizeof(pReg->pullsel)/sizeof(pReg->pullsel[0]); idx++)
297 cur->pullsel[idx].val =GPIO_RD32(&pReg->pullsel[idx]);
298 #endif
299 for (idx = 0; idx < sizeof(pReg->dout)/sizeof(pReg->dout[0]); idx++)
300 cur->dout[idx].val = GPIO_RD32(&pReg->dout[idx]);
301 for (idx = 0; idx < sizeof(pReg->mode)/sizeof(pReg->mode[0]); idx++)
302 cur->mode[idx].val = GPIO_RD32(&pReg->mode[idx]);
303 #endif
304 }
305 /*----------------------------------------------------------------------------*/
306 EXPORT_SYMBOL(mt_gpio_checkpoint_save);
307 /*----------------------------------------------------------------------------*/
308 void mt_gpio_dump_diff(GPIO_REGS* pre, GPIO_REGS* cur)
309 {
310 #if defined(GPIO_INIT_DEBUG)
311 GPIO_REGS *pReg = (GPIO_REGS*)(GPIO_BASE);
312 int idx;
313 unsigned char* p = (unsigned char*)pre;
314 unsigned char* q = (unsigned char*)cur;
315
316 GPIOVER("------ dumping difference between %p and %p ------\n", pre, cur);
317 for (idx = 0; idx < sizeof(pReg->dir)/sizeof(pReg->dir[0]); idx++) {
318 if (pre->dir[idx].val != cur->dir[idx].val)
319 GPIOVER("diff: dir[%2d] : 0x%08X <=> 0x%08X\n", idx, pre->dir[idx].val, cur->dir[idx].val);
320 }
321 #if 0
322 for (idx = 0; idx < sizeof(pReg->pullen)/sizeof(pReg->pullen[0]); idx++) {
323 if (pre->pullen[idx].val != cur->pullen[idx].val)
324 GPIOVER("diff: pullen[%2d] : 0x%08X <=> 0x%08X\n", idx, pre->pullen[idx].val, cur->pullen[idx].val);
325 }
326 for (idx = 0; idx < sizeof(pReg->pullsel)/sizeof(pReg->pullsel[0]); idx++) {
327 if (pre->pullsel[idx].val != cur->pullsel[idx].val)
328 GPIOVER("diff: pullsel[%2d]: 0x%08X <=> 0x%08X\n", idx, pre->pullsel[idx].val, cur->pullsel[idx].val);
329 }
330 #endif
331 for (idx = 0; idx < sizeof(pReg->dout)/sizeof(pReg->dout[0]); idx++) {
332 if (pre->dout[idx].val != cur->dout[idx].val)
333 GPIOVER("diff: dout[%2d] : 0x%08X <=> 0x%08X\n", idx, pre->dout[idx].val, cur->dout[idx].val);
334 }
335 for (idx = 0; idx < sizeof(pReg->mode)/sizeof(pReg->mode[0]); idx++) {
336 if (pre->mode[idx].val != cur->mode[idx].val)
337 GPIOVER("diff: mode[%2d] : 0x%08X <=> 0x%08X\n", idx, pre->mode[idx].val, cur->mode[idx].val);
338 }
339
340 for (idx = 0; idx < sizeof(*pre); idx++) {
341 if (p[idx] != q[idx])
342 GPIOVER("diff: raw[%2d]: 0x%02X <=> 0x%02X\n", idx, p[idx], q[idx]);
343 }
344 GPIOVER("memcmp(%p, %p, %d) = %d\n", p, q, sizeof(*pre), memcmp(p, q, sizeof(*pre)));
345 GPIOVER("------ dumping difference end --------------------------------\n");
346 #endif
347 }
348 /*----------------------------------------------------------------------------*/
349 void mt_gpio_checkpoint_compare(void)
350 {
351 #if defined(GPIO_INIT_DEBUG)
352 GPIO_REGS *pReg = (GPIO_REGS*)(GPIO_BASE);
353 GPIO_REGS latest;
354 GPIO_REGS *cur = &latest;
355 int idx;
356
357 memset(cur, 0x00, sizeof(*cur));
358 for (idx = 0; idx < sizeof(pReg->dir)/sizeof(pReg->dir[0]); idx++)
359 cur->dir[idx].val = GPIO_RD32(&pReg->dir[idx]);
360 #if 0
361 for (idx = 0; idx < sizeof(pReg->pullen)/sizeof(pReg->pullen[0]); idx++)
362 cur->pullen[idx].val = GPIO_RD32(&pReg->pullen[idx]);
363 for (idx = 0; idx < sizeof(pReg->pullsel)/sizeof(pReg->pullsel[0]); idx++)
364 cur->pullsel[idx].val =GPIO_RD32(&pReg->pullsel[idx]);
365 #endif
366 for (idx = 0; idx < sizeof(pReg->dout)/sizeof(pReg->dout[0]); idx++)
367 cur->dout[idx].val = GPIO_RD32(&pReg->dout[idx]);
368 for (idx = 0; idx < sizeof(pReg->mode)/sizeof(pReg->mode[0]); idx++)
369 cur->mode[idx].val = GPIO_RD32(&pReg->mode[idx]);
370
371 //mt_gpio_dump_diff(&latest, &saved);
372 //GPIODBG("memcmp(%p, %p, %d) = %d\n", &latest, &saved, sizeof(GPIO_REGS), memcmp(&latest, &saved, sizeof(GPIO_REGS)));
373 if (memcmp(&latest, &saved, sizeof(GPIO_REGS))) {
374 GPIODBG("checkpoint compare fail!!\n");
375 GPIODBG("dump checkpoint....\n");
376 //mt_gpio_dump(&saved);
377 GPIODBG("\n\n");
378 GPIODBG("dump current state\n");
379 //mt_gpio_dump(&latest);
380 GPIODBG("\n\n");
381 mt_gpio_dump_diff(&saved, &latest);
382 //WARN_ON(1);
383 } else {
384 GPIODBG("checkpoint compare success!!\n");
385 }
386 #endif
387 }
388 /*----------------------------------------------------------------------------*/
389 EXPORT_SYMBOL(mt_gpio_checkpoint_compare);
390 /*----------------------------------------------------------------------------*/
391 #endif
392 #endif
393
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