module vga_colorbar (
input wire sys_clk, // 输入系统时钟，50MHz
input wire sys_rst_n, // 系统复位信号，低电平有效
input wire key, //按键输入信号
input wire shift, //按键输入信号
output wire hsync, // 行同步信号
output wire vsync, // 场同步信号
output wire [2:0] rgb, // 输出RGB像素数据
input key_stop ,
input key_choose ,
input key_add ,
input rx,
output beep ,
output [3:0] data0 ,
output [3:0] data1 ,
output [3:0] data2 ,
output [3:0] data3 ,
output [3:0] data4 ,
output [3:0] data5 ,
output led0,
output led1,
output tx
);
wire vga_clk; // VGA工作时钟，25MHz
wire locked; // PLL锁定信号
wire rst_n; // 复位信号
wire [9:0] pix_x; // 像素X轴坐标
wire [9:0] pix_y; // 像素Y轴坐标
wire [2:0] pix_data; // 像素数据
wire [1:0]mode; // 显示模式选择信号
//wire [5:0] seconds; // 秒
//wire [5:0] minutes; // 分钟
//wire [4:0] hours; // 小时
wire clk_8hz;
wire stop ;
wire [2:0] choose ;
wire flag_1s;
wire [5:0] second;
wire [5:0] minute;
wire [4:0] hour ;
wire [5:0] alarm_second;
wire [5:0] alarm_minute;
wire [4:0] alarm_hour ;
wire beeps;
wire [3:0] da0;
wire [3:0] da1;
wire [3:0] da2;
wire [3:0] da3;
wire [3:0] da4;
wire [3:0] da5;
wire [7:0] po_data;
wire po_flag;
parameter UART_BPS = 14'd9600; //比特率
parameter CLK_FREQ = 26'd50_000_000; //时钟频率
assign rst_n = sys_rst_n & locked;
// PLL时钟生成模块
clk_gen clk_gen_inst (
.areset(~sys_rst_n),
.inclk0(sys_clk),
.c0(vga_clk),
.locked(locked)
);
// VGA控制模块
vga_ctrl vga_ctrl_inst (
.vga_clk(vga_clk),
.sys_rst_n(rst_n),
.pix_data(pix_data),
.pix_x(pix_x),
.pix_y(pix_y),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb)
);
// 按键控制模块
//key_control key_control_inst (
// .clk(clk_8hz),
// .key(key),
// .mode(mode)
//);
// 实例化时钟生成模块
//clock_gen u_clock_gen (
// .clk(sys_clk),
// .reset(rst_n),
// .seconds(seconds),
// .minutes(minutes),
// .hours(hours)
//);
// 生成模块
vga_pic vga_pic_inst (
.vga_clk(vga_clk),
.sys_rst_n(rst_n),
.pix_x(pix_x),
.pix_y(pix_y),
.mode(mode),
.pix_data_out(pix_data),
.hr_units(data1),
.hr_tens(data0),
.min_tens(data2),
.min_units(data3),
.sec_tens(data4),
.sec_units(data5)
);
clk_8hz clk_8hz_0
(
.clk(sys_clk),
.clk_8hz(clk_8hz)
);
// 按键控制模块
kz kz_0(
.clk (clk_8hz ), //input clk ,
.key_stop (key_stop ), //input key_stop ,
.key_choose (key_choose ), //input key_choose ,
.key_vga (key ),
.mode (mode ),
.stop (stop ), //output reg stop ,
.choose (choose ), //output reg [2:0] choose ,
.rs232_signal (po_flag)
);
clk_1s clk_1s_0(
.clk (clk_8hz ), //input clk ,
.stop (stop ), //input stop ,
.flag_1s (flag_1s) //output flag_1s
);
clock clock_0(
.clk (clk_8hz ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.flag_add (key_add ), //input flag_add ,
.flag_1s (flag_1s ), //input flag_1s ,
.second (second ), //output reg [5:0] second ,
.minute (minute ), //output reg [5:0] minute ,
.hour (hour ) //output reg [4:0] hour
);
alarm_clock alarm_clock_0(
.clk (clk_8hz ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.flag_add (key_add ), //input flag_add ,
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.alarm_second (alarm_second ), //output reg [5:0] alarm_second ,
.alarm_minute (alarm_minute ), //output reg [5:0] alarm_minute ,
.alarm_hour (alarm_hour ), //output reg [4:0] alarm_hour ,
.beep (beeps ) //output beep
);
digital_display digital_display_0(
.clk (sys_clk ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.shift (shift ),
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.alarm_second (alarm_second), //input [5:0] alarm_second ,
.alarm_minute (alarm_minute), //input [5:0] alarm_minute ,
.alarm_hour (alarm_hour ), //input [4:0] alarm_hour ,
.data0 (data0 ), //output reg [3:0] data0 ,
.data1 (data1 ), //output reg [3:0] data1 ,
.data2 (data2 ), //output reg [3:0] data2 ,
.data3 (data3 ), //output reg [3:0] data3 ,
.data4 (data4 ), //output reg [3:0] data4 ,
.data5 (data5 ), //output reg [3:0] data5
.led0 (led0),
.led1 (led1)
);
digital_display digital_display_1(
.clk (sys_clk ), //input clk ,
.stop (stop ), //input stop ,
.choose (choose ), //input [2:0] choose ,
.shift (shift ),
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.alarm_second (alarm_second), //input [5:0] alarm_second ,
.alarm_minute (alarm_minute), //input [5:0] alarm_minute ,
.alarm_hour (alarm_hour ), //input [4:0] alarm_hour ,
.data0 (da0 ), //output reg [3:0] data0 ,
.data1 (da1 ), //output reg [3:0] data1 ,
.data2 (da2 ), //output reg [3:0] data2 ,
.data3 (da3 ), //output reg [3:0] data3 ,
.data4 (da4 ), //output reg [3:0] data4 ,
.data5 (da5 ) //output reg [3:0] data5
);
beep beep_0(
.sys_clk (sys_clk ), //input clk ,
.sys_rst_n (key ), //input key_rt ,
.stop (stop ), //input stop ,
.beep (beeps ), //input beep ,
.second (second ), //input [5:0] second ,
.minute (minute ), //input [5:0] minute ,
.hour (hour ), //input [4:0] hour ,
.ring (beep ), //output ring ,
.flag_1s (flag_1s ) //output flag_1s ,
);
uart_rx
#(
.UART_BPS (UART_BPS), //串口波特率
.CLK_FREQ (CLK_FREQ) //时钟频率
)
uart_rx_inst
(
.sys_clk (sys_clk ), //input sys_clk
.sys_rst (!key_stop ), //input sys_rst_n
.rx (rx ), //input rx
.po_data (po_data ), //output [7:0] po_data
.po_flag (po_flag ) //output po_flag
);
uart_tx
#(
.UART_BPS (UART_BPS), //串口波特率
.CLK_FREQ (CLK_FREQ) //时钟频率
)
uart_tx_inst
(
.sys_clk (sys_clk ), //input sys_clk
.sys_rst (!key_stop ), //input sys_rst_n
.pi_data (po_data ), //input [7:0] pi_data
.pi_flag (po_flag ), //input pi_flag
.tx (tx ) //output tx
);
endmodule
module alarm_clock(
input clk ,
input stop ,
input [2:0] choose ,
input flag_add ,
input flag_subtract,
input [5:0] second ,
input [5:0] minute ,
input [4:0] hour ,
output reg [5:0] alarm_second ,
output reg [5:0] alarm_minute ,
output reg [4:0] alarm_hour ,
output beep
);
initial
begin
alarm_hour<=4;
alarm_minute<=1;
alarm_second<=0;
end
always@(posedge clk)
begin
if(stop && choose == 3)begin
if(alarm_hour == 23 && flag_add)begin
alarm_hour <= 0;
end else if(flag_add)begin
alarm_hour <= alarm_hour+1;
end else begin
alarm_hour <= alarm_hour;
end
end
end
always@(posedge clk)
begin
if(stop && choose == 4)begin
if(alarm_minute == 59 && flag_add)begin
alarm_minute <= 0;
end else if(flag_add)begin
alarm_minute <= alarm_minute+1;
end else begin
alarm_minute <= alarm_minute;
end
end
end
always@(posedge clk)
begin
if(stop && choose == 5)begin
if(alarm_second == 59 && flag_add)begin
alarm_second <= 0;
end else if(flag_add)begin
alarm_second <= alarm_second+1;
end else begin
alarm_second <= alarm_second;
end
end
end
assign beep = (!stop) ? ((alarm_hour == hour && alarm_minute == minute) ? 1 : 0) : 0;
endmodule
module clock(
input clk ,
input stop ,
input [2:0] choose ,
input flag_add ,
input flag_1s ,
output reg [5:0] second ,
output reg [5:0] minute ,
output reg [4:0] hour
);
initial
begin
hour<=3;
minute<=59;
second<=50;
end
always@(posedge clk)
begin
if(stop && choose == 2)begin
if(second == 59 && flag_add)begin
second <= 0;
end else if(flag_add)begin
second <= second+1;
end else begin
second <= second;
end
end else begin
if(second == 59 && flag_1s)begin
second <= 0;
end else if(flag_1s)begin
second <= second+1;
end else begin
second <= second;
end
end
end
always@(posedge clk)
begin
if(stop && choose == 1)begin
if(minute == 59 && flag_add)begin
minute <= 0;
end else if(flag_add)begin
minute <= minute+1;
end else begin
minute <= minute;
end
end else begin
if(minute == 59 && second == 59 && flag_1s)begin
minute <= 0;
end else if(second == 59 && flag_1s)begin
minute <= minute+1;
end else begin
minute <= minute;
end
end
end
always@(posedge clk)
begin
if(stop && choose == 0)begin
if(hour == 23 && flag_add)begin
hour <= 0;
end else if(flag_add)begin
hour <= hour+1;
end else begin
hour <= hour;
end
end else begin
if(hour == 23 && minute == 59 && second == 59 && flag_1s)begin
hour <= 0;
end else if(minute == 59 && second == 59 && flag_1s)begin
hour <= hour+1;
end else begin
hour <= hour;
end
end
end
endmodule
module digital_display(
input clk ,
input stop ,
input shift ,
input [2:0] choose ,
input [5:0] second ,
input [5:0] minute ,
input [4:0] hour ,
input [5:0] alarm_second ,
input [5:0] alarm_minute ,
input [4:0] alarm_hour ,
output reg [3:0] data0 ,
output reg [3:0] data1 ,
output reg [3:0] data2 ,
output reg [3:0] data3 ,
output reg [3:0] data4 ,
output reg [3:0] data5 ,
output reg led0 ,
output reg led1
);
reg [4:0] hour_shift;//12进制
reg a;
always@(posedge clk)
begin
case(hour)
0:begin hour_shift<=12;led0=0; end
1:begin hour_shift<=1;led0=0; end
2:begin hour_shift<=2;led0=0; end
3:begin hour_shift<=3;led0=0; end
4:begin hour_shift<=4;led0=0; end
5:begin hour_shift<=5;led0=0; end
6:begin hour_shift<=6;led0=0; end
7:begin hour_shift<=7;led0=0; end
8:begin hour_shift<=8;led0=0; end
9:begin hour_shift<=9;led0=0; end
10:begin hour_shift<=10;led0=0; end
11:begin hour_shift<=11;led0=0; end
12:begin hour_shift<=12;led0=1; end
13:begin hour_shift<=1;led0=1; end
14:begin hour_shift<=2;led0=1; end
15:begin hour_shift<=3;led0=1; end
16:begin hour_shift<=4;led0=1; end
17:begin hour_shift<=5;led0=1; end
18:begin hour_shift<=6;led0=1; end
19:begin hour_shift<=7;led0=1; end
20:begin hour_shift<=8;led0=1; end
21:begin hour_shift<=9;led0=1; end
22:begin hour_shift<=10;led0=1; end
23:begin hour_shift<=11;led0=1; end
endcase
end
reg [25:0] cnt_300ms;
parameter num_300ms = 7499999;
reg clk_300ms;
always@(posedge clk)
begin
if(cnt_300ms == num_300ms)begin
cnt_300ms <= 0;
clk_300ms <= !clk_300ms;
end else begin
cnt_300ms <= cnt_300ms+1;
clk_300ms <= clk_300ms;
end
end
always@(posedge clk)
begin
if(stop)begin
if(shift)begin
case(choose)
0:begin
if(clk_300ms)begin
data0 <= 4'hf;
data1 <= 4'hf;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end else begin
data0 <= hour_shift/10;
data1 <= hour_shift%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
1:begin
if(clk_300ms)begin
data0 <= hour_shift/10;
data1 <= hour_shift%10;
data2 <= 4'hf;
data3 <= 4'hf;
data4 <= second/10;
data5 <= second%10;
end else begin
data0 <= hour_shift/10;
data1 <= hour_shift%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
2:begin
if(clk_300ms)begin
data0 <= hour_shift/10;
data1 <= hour_shift%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= 4'hf;
data5 <= 4'hf;
end else begin
data0 <= hour_shift/10;
data1 <= hour_shift%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
3:begin
if(clk_300ms)begin
data0 <= 4'hf;
data1 <= 4'hf;
data2 <= alarm_minute/10;
data3 <= alarm_minute%10;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end else begin
data0 <= alarm_hour/10;
data1 <= alarm_hour%10;
data2 <= alarm_minute/10;
data3 <= alarm_minute%10;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end
end
4:begin
if(clk_300ms)begin
data0 <= alarm_hour/10;
data1 <= alarm_hour%10;
data2 <= 4'hf;
data3 <= 4'hf;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end else begin
data0 <= alarm_hour/10;
data1 <= alarm_hour%10;
data2 <= alarm_minute/10;
data3 <= alarm_minute%10;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end
end
endcase
end else begin
case(choose)
0:begin
if(clk_300ms)begin
data0 <= 4'hf;
data1 <= 4'hf;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end else begin
data0 <= hour/10;
data1 <= hour%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
1:begin
if(clk_300ms)begin
data0 <= hour/10;
data1 <= hour%10;
data2 <= 4'hf;
data3 <= 4'hf;
data4 <= second/10;
data5 <= second%10;
end else begin
data0 <= hour/10;
data1 <= hour%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
2:begin
if(clk_300ms)begin
data0 <= hour/10;
data1 <= hour%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= 4'hf;
data5 <= 4'hf;
end else begin
data0 <= hour/10;
data1 <= hour%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
3:begin
if(clk_300ms)begin
data0 <= 4'hf;
data1 <= 4'hf;
data2 <= alarm_minute/10;
data3 <= alarm_minute%10;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end else begin
data0 <= alarm_hour/10;
data1 <= alarm_hour%10;
data2 <= alarm_minute/10;
data3 <= alarm_minute%10;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end
end
4:begin
if(clk_300ms)begin
data0 <= alarm_hour/10;
data1 <= alarm_hour%10;
data2 <= 4'hf;
data3 <= 4'hf;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end else begin
data0 <= alarm_hour/10;
data1 <= alarm_hour%10;
data2 <= alarm_minute/10;
data3 <= alarm_minute%10;
data4 <= alarm_second/10;
data5 <= alarm_second%10;
end
end
endcase
end
end else begin
if(shift)begin
data0 <= hour_shift/10;
data1 <= hour_shift%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end else begin
data0 <= hour/10;
data1 <= hour%10;
data2 <= minute/10;
data3 <= minute%10;
data4 <= second/10;
data5 <= second%10;
end
end
end
endmodule module kz(
input clk ,
input key_stop ,
input key_choose ,
input key_vga ,
input rs232_signal,
output reg [1:0] mode ,
output reg stop ,
output reg [2:0] choose
);
always@(posedge clk)
begin
if(key_stop)begin
stop <= 0;
end else begin
stop <= 1;
end
end
always@(posedge clk or posedge rs232_signal )
begin
if(rs232_signal)
choose <= choose+1;
else
if(stop)begin
if(choose == 4 && key_choose)begin
choose <= 0;
end else if(key_choose)begin
choose <= choose+1;
end else begin
choose <= choose;
end
end else begin
choose <= 0;
end
end
always @(posedge clk)
begin
if(key_vga && mode==2)begin // 记录当前按键状态
mode<=0;
end else if(key_vga)begin
mode<=mode+1;
end else
mode<=mode;
end
endmodule module uart_rx
#(
parameter UART_BPS = 'd9600, //串口波特率
parameter CLK_FREQ = 'd50_000_000 //时钟频率
)
(
input wire sys_clk , //系统时钟50MHz
input wire sys_rst , //全局复位
input wire rx , //串口接收数据
output reg [7:0] po_data , //串转并后的8bit数据
output reg po_flag //串转并后的数据有效标志信号
);
//localparam define
localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ;
//reg define
reg rx_reg1 ;
reg rx_reg2 ;
reg rx_reg3 ;
reg start_nedge ;
reg work_en ;
reg [12:0] baud_cnt ;
reg bit_flag ;
reg [3:0] bit_cnt ;
reg [7:0] rx_data ;
reg rx_flag ;
//插入两级寄存器进行数据同步，用来消除亚稳态
//rx_reg1:第一级寄存器，寄存器空闲状态复位为1
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
rx_reg1 <= 1'b1;
else
rx_reg1 <= rx;
//rx_reg2:第二级寄存器，寄存器空闲状态复位为1
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
rx_reg2 <= 1'b1;
else
rx_reg2 <= rx_reg1;
//rx_reg3:第三级寄存器和第二级寄存器共同构成下降沿检测
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
rx_reg3 <= 1'b1;
else
rx_reg3 <= rx_reg2;
//start_nedge:检测到下降沿时start_nedge产生一个时钟的高电平
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
start_nedge <= 1'b0;
else if((~rx_reg2) && (rx_reg3))
start_nedge <= 1'b1;
else
start_nedge <= 1'b0;
//work_en:接收数据工作使能信号
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
work_en <= 1'b0;
else if(start_nedge == 1'b1)
work_en <= 1'b1;
else if((bit_cnt == 4'd8) && (bit_flag == 1'b1))
work_en <= 1'b0;
//baud_cnt:波特率计数器计数，从0计数到5207
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
baud_cnt <= 13'b0;
else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0))
baud_cnt <= 13'b0;
else if(work_en == 1'b1)
baud_cnt <= baud_cnt + 1'b1;
//bit_flag:当baud_cnt计数器计数到中间数时采样的数据最稳定，
//此时拉高一个标志信号表示数据可以被取走
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
bit_flag <= 1'b0;
else if(baud_cnt == BAUD_CNT_MAX/2 - 1)
bit_flag <= 1'b1;
else
bit_flag <= 1'b0;
//bit_cnt:有效数据个数计数器，当8个有效数据（不含起始位和停止位）
//都接收完成后计数器清零
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
bit_cnt <= 4'b0;
else if((bit_cnt == 4'd8) && (bit_flag == 1'b1))
bit_cnt <= 4'b0;
else if(bit_flag ==1'b1)
bit_cnt <= bit_cnt + 1'b1;
//rx_data:输入数据进行移位
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
rx_data <= 8'b0;
else if((bit_cnt >= 4'd1)&&(bit_cnt <= 4'd8)&&(bit_flag == 1'b1))
rx_data <= {rx_reg3, rx_data[7:1]};
//rx_flag:输入数据移位完成时rx_flag拉高一个时钟的高电平
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
rx_flag <= 1'b0;
else if((bit_cnt == 4'd8) && (bit_flag == 1'b1))
rx_flag <= 1'b1;
else
rx_flag <= 1'b0;
//po_data:输出完整的8位有效数据
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
po_data <= 8'b0;
else if(rx_flag == 1'b1)
po_data <= rx_data;
//po_flag:输出数据有效标志（比rx_flag延后一个时钟周期，为了和po_data同步）
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
po_flag <= 1'b0;
else
po_flag <= rx_flag;
endmodule module uart_tx
#(
parameter UART_BPS = 'd9600, //串口波特率
parameter CLK_FREQ = 'd50_000_000 //时钟频率
)
(
input wire sys_clk , //系统时钟50MHz
input wire sys_rst , //全局复位
input wire [7:0] pi_data , //模块输入的8bit数据
input wire pi_flag , //并行数据有效标志信号
output reg tx //串转并后的1bit数据
);
////
//\* Parameter and Internal Signal \//
////
//localparam define
localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ;
//reg define
reg [12:0] baud_cnt;
reg bit_flag;
reg [3:0] bit_cnt ;
reg work_en ;
////
//\* Main Code \//
////
//work_en:接收数据工作使能信号
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
work_en <= 1'b0;
else if(pi_flag == 1'b1)
work_en <= 1'b1;
else if((bit_flag == 1'b1) && (bit_cnt == 4'd9))
work_en <= 1'b0;
//baud_cnt:波特率计数器计数，从0计数到5207
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
baud_cnt <= 13'b0;
else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0))
baud_cnt <= 13'b0;
else if(work_en == 1'b1)
baud_cnt <= baud_cnt + 1'b1;
//bit_flag:当baud_cnt计数器计数到1时让bit_flag拉高一个时钟的高电平
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
bit_flag <= 1'b0;
else if(baud_cnt == 13'd1)
bit_flag <= 1'b1;
else
bit_flag <= 1'b0;
//bit_cnt:数据位数个数计数，10个有效数据（含起始位和停止位）到来后计数器清零
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
bit_cnt <= 4'b0;
else if((bit_flag == 1'b1) && (bit_cnt == 4'd9))
bit_cnt <= 4'b0;
else if((bit_flag == 1'b1) && (work_en == 1'b1))
bit_cnt <= bit_cnt + 1'b1;
//tx:输出数据在满足rs232协议（起始位为0，停止位为1）的情况下一位一位输出
always@(posedge sys_clk or negedge sys_rst)
if(sys_rst == 1'b0)
tx <= 1'b1; //空闲状态时为高电平
else if(bit_flag == 1'b1)
case(bit_cnt)
0 : tx <= 1'b0;
1 : tx <= pi_data[0];
2 : tx <= pi_data[1];
3 : tx <= pi_data[2];
4 : tx <= pi_data[3];
5 : tx <= pi_data[4];
6 : tx <= pi_data[5];
7 : tx <= pi_data[6];
8 : tx <= pi_data[7];
9 : tx <= 1'b1;
default : tx <= 1'b1;
endcase
endmodule 设计串口通信代码，保留蜂鸣器，时钟，按键，通过按键设置时钟闹钟时间等等的功能，，根据下面的思路修改我的代码，命名与我的代码一致。增加rs232扩展实现上位机设置fpga开发板的闹钟时分秒，时钟时分秒，12/24时制转换。串口通信接收到上位机信息例如‘0’‘1’‘2’‘3’‘4’‘等时，相关信号数值做相应改变，实现控制相应功能
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