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r To access RTC Time Count Read Register (RTCCNTREAD) and RTC Time Count Setting Register (RTCCNTWRITE), the RTCCTRL.RTCCNTWRITEENB bit is set to "1" before accessing these register. When the CPU completes to access these register, the CPU should set the RTCCTRL.RTCCNTWRITEENB bit to "0" to protect the content of RTC counter from unknown problem in abnormal state. The RTCCNTWRITEENB bit determines the reflection of the RCCNTWRITE register value to the RTC counter. 12.4.4 Interrupt Pending Register Only the "READ" function is available for the RTCINTPND register of the S5P6818, but the current pending status can be read. Since the RTCINTPND register only has a "READ" function, the Pending Clear function is controlled by the RTCINTENB register. The Interrupt Pending status is cleared by disabling the relevant interrupt. Therefore, if the corresponding bit of the RTCINTENB register is set as "1", the relevant interrupt is enabled. If the corresponding bit is set as "0", the interrupt is disabled and the pending bit is also cleared. 12.4.5 Power Manager Reset Time Control RTC controls the time when nPWRMANRST (Power Manager Reset) releases from CorePOR. Refer to RTCCORERSTIMESEL Register for setting the time when nPWRMANRST releases