Partitioning for Synthesis

最新推荐文章于 2025-02-11 15:05:46 发布

转载最新推荐文章于 2025-02-11 15:05:46 发布 · 521 阅读

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#asic verilog

本文介绍了一种基于“分而治之”的概念来简化复杂设计的方法——设计分区，并提供了实现最佳综合效果及缩短编译时间的一系列建议。这些策略包括保持相关组合逻辑在同一模块内、按功能划分模块、限制合理区块大小等。

Partitioning can be viewed as, utilizing the “Divide and Conquer” concept to reduce complex designs into simpler and manageable blocks. Promoting design reuse is one of the most significant advantages to partitioning the design.

Apart from the ease in meeting timing constraints for a properly partitioned design, it is also convenient to distribute and manage different blocks of the design between team members.

The following recommendations achieve best synthesis results and reduction in compile time.

a) Keep related combinational logic in the same module.
b) Partition for design reuse.
c) Separate modules according to their functionality.
d) Separate structural logic from random logic.
e) Limit a reasonable block size (depends on the memory capacity of the machine)
f) Partition the top level (separate I/O Pads, Boundary Scan and core logic).
g) Do not add glue-logic at the top level.
h) Isolate state-machine from other logic.
i) Avoid multiple clocks within a block.
j) Isolate the block that is used for synchronizing multiple clocks.
k) WHILE PARTITIONING, THINK OF YOUR LAYOUT STYLE.