Multithreaded Game Programming and Hyper-Threading Technology

Microarchitecture: HyperThreading(超线程) 线程并行 当代的软件趋向于运行在多线程模式,或者是并行处理。网络包传输和web服务可以运行以多线程的方式运行以达到更高的性能。甚至是桌面应用也开始增加并行性。Intel架构师已经开始尝试利用TLP( thread-level parallelism) 线程并行性,用来在较少的晶体管和功耗下就能达到更高的性能。 高端和终端的服务器市场,多核已经被广泛的使用,已获得更高的性能。通过增加处理器,应用... 阅读详情
Multithreaded Game Programming and Hyper-Threading Technology
Published On: Tuesday, July 24, 2007 | Last Modified On: Tuesday, July 24, 2007
Overview
By Will Damon

Multiprocessor machines are becoming more commonplace on the desktop with the introduction of  Hyper-Threading Technology to the Intel® Pentium® 4 processor. While multithreaded programming is not new to games, the widespread adoption of multiprocessor machines means that programmers can seriously consider the threaded performance of algorithms, and software system design. This paper aims to introduce the two domains of threading methodology as they apply to game development, and address the most common pitfalls of game programming for Hyper-Threading Technology (HT) enabled systems.

Parallel Models

Parallelism, the simultaneous processing of different data or tasks, is achieved through two models: data- and functional- decomposition (also known as data and task parallelism). As the names imply, these two models represent very different yet complementary methods of applying multiple threads to achieve a higher level of performance within a single process (like a game). Each parallel model has its own section below; data decomposition is covered first, followed by functional decomposition.


Data Decomposition
Data decomposition means that the same independent operation is applied to different data. Compute-intensive loops, like those found in game physics simulation solvers, for example, are good candidates for data parallelization. Each game has different situations in which data parallelism applies, but just for illustration, here is a short list that is by no means exhaustive:

  • Generating procedural terrain, textures, or geometry
  • Physics solvers (for collision, behavior, and even sound)
  • Skinning and/or animation
  • Various artificial intelligence algorithms
  • Path finding
  • Audio processing
Many other applications are also possible. The trick is determining when to use threads to implement parallel computation for higher performance.

The easiest way to find an area in a game that might benefit from data decomposition is to profile the game on a multiprocessor or HT-enabled system. The Intel® VTune™ Performance Analyzer is great for this because it tells exactly how much time is spent idle, as well as how much time running threads are consuming of each logical processor. A profile of a game on an HT-enabled system will give a clear indication of where the whole system is spending time, and how well the workload is balanced. Focusing on the heaviest time-consuming modules will point you to which modules may benefit from data decomposition, not to mention highlighting serial optimization opportunities, too. While threading can improve performance, additional wins may be achieved with other Intel® NetBurst™ microarchitecture optimizations. See item [11] in the Additional Resources section for more information on NetBurst microarchitecture optimizations.


Functional Decomposition
Functional decomposition works at a higher level than data decomposition. In functional decomposition, also known as task-parallelism, independent work is mapped to asynchronous threads. This model applies to games particularly well because there are typically so many different subsystems executing simultaneously. Some professional game developers have been threading their games for years, spawning threads to handle various subsystems, well before the introduction of Hyper-Threading Technology on the desktop. The advantage of functionally decomposing a game today, however, reaches beyond the scope of programmer convenience. Threads can run concurrently on HT-enabled hardware, yielding higher performance and more responsiveness; something which end users will appreciate. Additionally, having one ready-to-run thread per logical processor means that your game can consume idle processor cycles, again working towards higher performance. The number of ways in which you can separate subsystems is infinite; however, always keep in mind the general rule of thumb for multithreaded programming: make sure running threads conflict as little as possible!

A quick example to illustrate one possible approach to threading a game engine is to allow separate threads to handle the following subsystems:

  • Asynchronous Streaming (I/O)
  • AI
  • Audio
  • Input
  • Network
  • Physics
  • Rendering
  • UI
  • Other subsystems (video playback, garbage collection, etc.)
Potentially, it could make sense to combine some of these together into a single thread, but the idea is the same - separate decoupled systems into asynchronous threads for higher performance and more responsiveness in multithreading desktop environments. Threading your engine may allow you to do some interesting things that could potentially degrade performance on a serial (single-threaded) model, like execute more complex AI or run larger physics simulations. Additionally, depending on your game, threading might allow you to more easily run various decoupled subsystems at different refresh rates (e.g. physics at 100Hz, graphics at 60 Hz), yielding a smoother experience in a richer game environment for your players.


Three Threading Models
Understanding parallelism and how it may be applied are important, but knowing how it is most effectively implemented is equally important. The next three sections each discuss one of the three approaches to achieve parallelism; they are ordered from least invasive to most invasive in terms of the code base and time investment.

Automatic Parallelization

The simplest means of parallelizing loops (data decomposition) is to let the compiler do all the work for you. The Intel C++ Compiler, version 7.0 and later, has support to analyze loops and parallelize those that it considers good candidates. The -Qparallel switch enables the feature, and following a few simple guidelines increases the likelihood that the compiler will identify a parallel loop.

  • First, expose the trip count of the loop. This does not mean defining the trip count as a compiler directive. This means that the compiler must be able to determine whether the trip count varies during loop execution. For example, altering a for-loop counter inside the loop body could violate this first rule, and the compiler may not identify the loop as parallel.
  • Next, avoid branching from the loop. Branching can have a similar effect to failing the first guideline (expose trip count), in which the compiler cannot determine whether the loop is a parallel candidate.
  • The third guideline is to avoid referencing global data or procedure calls from within the loop body. The compiler cannot guarantee correct parallel execution on the volatile elements, so loops with such references may not generate parallel code. However, referencing a pure function, a function which has no side effects, does not disrupt parallelism.
Failure to adhere to these guidelines does not automatically disqualify a loop from automatic parallelization. Use the -Qpar_report3 switch to have the compiler generate a report on which loops were successfully parallelized and the dependencies that prevent parallelization of others. ( -Qpar_report[n] will allow varying degrees of reporting.)

Compiler-directed Parallelism with OpenMP

While automatic parallelization is great, there are times when the developer can, or would like to direct the compiler what to thread. After all, you know much more about the overlying algorithm than the compiler could ever attempt to understand. The OpenMP standard allows the developer the kind of flexibility s/he desires, while limiting the time investment necessary to thread code. OpenMP works on an explicit fork/join method, so the programmer must specify the start and end of a parallel region.

The Intel C++ Compiler version 7.0 supports OpenMP, but not all C++ compilers at the time of this writing do so. Use the -Qopenmp switch to enable processing of the OpenMP directives or pragmas to generate threaded code. Without this switch, the Intel C++ Compiler will do the same thing as compilers that do not support OpenMP, and simply ignore the directives.

The cool thing about OpenMP is that it allows easy parallelization of loops or regions of your code without large-scale modifications. In fact, the original serial code is left largely intact. The following example that calculates a height field for a patch of terrain demonstrates:

#include <omp.h>

int TerrainManager::InitializePatches(D3DWrapper* pD3DWrapper, int PatchDivisions,
int SubPatchesX, int SubPatchesZ)
{
    int idx, z, x;

    if( PatchDivisions < 1 )
        PatchDivisions = 1;
    if( SubPatchesX < 1 )
        SubPatchesX = 1;
    if( SubPatchesZ < 1 )
        SubPatchesZ = 1;
   
    mPatchDivisions = PatchDivisions;

    mPatchesX = SubPatchesX;
    mPatchesZ = SubPatchesZ;

    mNumPatches = SubPatchesX * SubPatchesZ;
    mpPatches = new TerrainPatchLOD*[mNumPatches];

#pragma omp parallel
    {
        float fScaleX = 1.0f / (float)SubPatchesX;
        float fScaleZ = 1.0f / (float)SubPatchesZ;

        Vector3 tPos1, tPos2;
        tPos1.Y = tPos2.Y = 0.0f;

#pragma omp for private(idx)
        for (z=0; z<SubPatchesZ; z++)
        {
            tPos2.Z = float(SubPatchesZ/2-z);
            for (x=0; x<SubPatchesX; x++)
            {
                tPos2.X = float(x - SubPatchesX / 2);
                idx = z*SubPatchesX + x;

                mpPatches[idx] = new TerrainPatchLOD( mFlags, mSeed );
                mpPatches[idx]->UseLOD(true); //use lowerLOD patches
                              where there is no override

                mpPatches[idx]->SetScale( Vector3( fScaleX, fScaleX, fScaleZ ) );
                tPos1.X = -0.5f + fScaleX * (float)x + fScaleX / 2.0f;
                tPos1.Z =  0.5f - fScaleZ * (float)z - fScaleZ / 2.0f;
                mpPatches[idx]->SetPos( tPos1 );
                mpPatches[idx]->mUnscaledPosition = tPos2;
                mpPatches[idx]->SetTextureCoords( x * fScaleX,
                               fScaleX, 1.0f - (z+1) * fScaleZ, fScaleZ );
                mpPatches[idx]->Init( pWrapper, PatchDivisions );
#pragma omp critical
                AddChild( mpPatches[idx] );
            }
        }
    }

    //-- Complete initialization process

    return SUCCESS;
}

In the above example, the loop to generate all the terrain data is threaded with three short lines of OpenMP directives. Efficient parallelization is achieved with very minimal programming effort, and the function speeds up (versus the serial version) by a measurable factor on a Pentium 4 processor with Hyper-Threading Technology.

Thread Libraries

Last, but not least, the developer can use the thread libraries (e.g. Win32 threads, or pthreads) to drive explicitly defined threads. Thread libraries are flexible enough to address both data and functional decomposition, but using them for data decomposition is invasive, time consuming, and error-prone. Computations must be separated into functions that can be mapped to threads, and the work must be manually divided among the threads. Additionally, explicit synchronization must be added in order to guarantee correct results. To illustrate, we revisit the example from the previous section, and this time we'll thread it using Win32 threads:

/**
    In TerrainManager.h ...
*/
class TerrainManager
{
protected:
    CriticalSection TERRAIN_BUILD_CS;

    static DWORD WINAPI BuildNextHalfOf(LPVOID arg)
    {
        ((IawTerrainArray*)arg)->BuildHalfOf();
        return 0;
    }
};

/**
    In TerrainManager.cpp ...
*/
void TerrainManager::BuildHalfOf()
{
    static int c = 0;

    int startz, endz, idx;

    EnterCriticalSection(&TERRAIN_BUILD_CS);

    if (!c)
    {
        startz = 0;
        endz   = mPatchesZ / 2;
        c++;
    }
    else
    {
        startz = mPatchesZ / 2;
        endz   = mPatchesZ;
        c--;
    }

    LeaveCriticalSection(&TERRAIN_BUILD_CS);

    float fScaleX = 1.0f / (float)mPatchesX;
    float fScaleZ = 1.0f / (float)mPatchesZ;

    Vector3 tPos1, tPos2;
    tPos1.Y = tPos2.Y = 0.0f;

    for (int z = startz; z < endz; z++)
    {
        tPos2.Z = float(mPatchesZ / 2 - z);

        for (int x = 0; x < mPatchesX; x++)
        {
            tPos2.X = float(x - mPatchesX / 2);
            idx = z*mPatchesX + x;

            mpPatches[idx] = new TerrainPatchLOD( mFlags, mSeed );
            mpPatches[idx]->UseLOD(true);
            mpPatches[idx]->SetScale( Vector3( fScaleX, fScaleX, fScaleZ ) );

            tPos1.X = -0.5f + fScaleX * (float)x + fScaleX / 2.0f;
            tPos1.Z =  0.5f - fScaleZ * (float)z - fScaleZ / 2.0f;

            mpPatches[idx]->SetPos( tPos1 );
            mpPatches[idx]->mUnscaledPosition = tPos2;
            mpPatches[idx]->SetTextureCoords( x * fScaleX, fScaleX, 1.0f -
                          (z+1) * fScaleZ, fScaleZ );
            mpPatches[idx]->Init( mp_D3DWrapper, mPatchDivisions );

            EnterCriticalSection(&TERRAIN_BUILD_CS);
            AddChild( mpPatches[idx] );
            LeaveCriticalSection(&TERRAIN_BUILD_CS);
        }
    }
}

int TerrainManager::InitializePatches(D3DWrapper* pD3DWrapper,
int PatchDivisions, int SubPatchesX, int SubPatchesZ)
{
    mp_D3DWrapper = pD3DWrapper;

    if( PatchDivisions < 1 )
        PatchDivisions = 1;
    if( SubPatchesX < 1 )
        SubPatchesX = 1;
    if( SubPatchesZ < 1 )
        SubPatchesZ = 1;

    mPatchDivisions = PatchDivisions;

    mPatchesX = SubPatchesX;
    mPatchesZ = SubPatchesZ;

    mNumPatches = SubPatchesX * SubPatchesZ;
    mpPatches = new TerrainPatchLOD*[mNumPatches];

    InitializeCriticalSection(&TERRAIN_BUILD_CS);

    const int num_threads = 2; // Number of threads = logical processors

    HANDLE hThread[num_threads];
    for (int i = 0; i < num_threads; i++)
        hThread[i] = CreateThread( NULL,
                                   0,
                                   TerrainManager::BuildNextHalfOf,
                                   (LPVOID)this,
                                   0,
                                   NULL );

    float fScaleX = 1.0f / (float)SubPatchesX;
    float fScaleZ = 1.0f / (float)SubPatchesZ;

    //-- Complete initialization process

    WaitForMultipleObjects( num_threads,
                            hThread,
                            TRUE,
                            INFINITE );

    DeleteCriticalSection(&TERRAIN_BUILD_CS);

    for (int i = 0; i < num_threads; i++)
        CloseHandle(hThread[i]);

    return SUCCESS;
}

As you can see, there is a bit more code involved here to accomplish the same data decomposition as in the previous example. However, the benefit of the threading libraries is the powerful flexibility and direct programmer control they provide. Using the threaded libraries correctly is important. Notice here that we create and delete the thread handles in the same class method. Generally this is something you should avoid except in one-time initialization situations. Creating threads is expensive; therefore, if using the threading libraries, it is probably worthwhile to generate a thread pool during initialization, and set events to wake up threads to perform their tasks when necessary. When the threads finish their tasks, they can go back to a resting state, releasing hardware resources for other tasks. See items [1] and [12] in the Additional Resources section for more information on thread pools.


Coding for Hyper-Threading Technology
Whether you're developing for a high-end 4-way or 8-way Intel® Xeon® processor system or a Hyper-Threading Technology enabled Pentium® 4 processor-based desktop system, paying attention to how threads are executing is important. Employing techniques to achieve good load balancing, cache blocking, and general effective utilization of the hardware is very important on an HT-enabled processor because the two logical processors share common execution resources. This means that even though two threads are running concurrently, they are competing for some of the same hardware resources. Keep in mind some of the following common programming pitfalls when targeting a Hyper-Threading Technology system, and avoid hard-to-diagnose performance problems later on during the optimization cycle.

Synchronization

Make sure running threads conflict as little as possible!
For synchronization on variables that you know are going to be imminently available, a simple spin-wait loop may suffice. Be careful, though, because spin-waits can quickly become a hindrance on performance. A spin-wait locks up processor resources because it runs so efficiently, therefore stalling both logical processors. Inserting an assembly-level pause instruction can alleviate the detrimental effects of spin-waits, and looks like so:

// Tight spin-wait loop that can lead to performance issues
while (synch_var != some_val) { }

// Tight spin-wait loop with pause instruction;
// fixes performance issue from above
while (synch_var != some_val)
{
     _asm pause
}

The pause instruction hints to the processor that the loop is spin-wait, and inserts a momentary pause into execution to allow the processor resources to be freed up for the other logical processor. Another way to slow down the tight spin-wait is to put the waiting thread to sleep. Either use the ANSI standard sleep(), or the Win32 Sleep(). The argument for the ANSI standard sleep() is the number of seconds for the thread to sleep, while the Win32 Sleep() uses milliseconds. Use whichever makes more sense for your game.

// Tight spin-wait loop that sleeps one tenth of one second
while (synch_var != some_val) { Sleep(100); }

Lastly, when you know the thread will be waiting for some indeterminate amount of time, the best way to synchronize is to tell the OS what the thread is doing. Under Windows* using the thread blocking APIs (e.g. WaitForSingleObject(), WaitForMultipleObjects()) will let you do just that.

In addition to all the explicit synchronization your code is aware of, be careful of implicit synchronization. For example, allocating memory off the heap will cause synchronization to occur. Avoid such thread synchronization by using the thread local stack allocation API TlsAlloc() or _alloca(). Also be careful of accessing global variables, as doing so may also cause synchronization.

64k Alias Conflicts

A 64K-aliasing conflict happens when a virtual memory address references a cache line that is modulo 64 kilobytes apart from another cache line that already resides in the L1 cache (see item [10] in the Additional Resources section). If the VTune™ Analyzer reports a 64K-aliasing event number increase of 5x or more on an HT-enabled system versus the same system with Hyper-Threading Technology disabled, then it is likely possible to achieve a meaningful speedup by alleviating some of the 64K-aliasing pressure. Generally two cases cause such an impact when Hyper-Threading Technology is enabled versus not:

  • Thread stacks aligned on one and two megabyte boundaries
  • Threads accessing data structures which happen to fall 64K (or modulo 64K) apart
Avoid these two common pitfalls by following a couple of guidelines provided by item [10] in the Additional Resources section and reinforced with further explanation here. First, try adjusting thread stack allocation thereby changing the relative addresses between offending accesses. This is an important guideline because the Win32 default for thread stack allocation is on 1MB boundaries, and thus has the potential to cause serious performance penalties on HT-enabled systems. In the case of interleaving or interspersed loads and stores from the same 64KB address space, try doing multiple loads then multiple stores. As far as data structures are concerned, there are a few things to try. One is to simply have your memory allocator allocate structures of 68KB instead of 64KB. Alternatively, your memory allocator might pad and return random offsets that are multiples of 128 bytes (for cache-friendliness and avoiding stalls due to unaligned loads). Finally, for multiple arrays, pad those that are multiple of 64KB in size, especially those that are accessed with the same index, so that they will not be allocated contiguously in memory. The simplest way to pad arrays is to artificially increase their sizes, or interleave their declarations with the declaration of other variables.

For more information about 64K-aliasing and how to avoid it see items [10] and [11] in the Additional Resources section.


Effective Cache Usage and Locality
Effective cache utilization is critical to top-end performance on both single- and multi-threading processors. Two common issues related to the cache that occur with multithreaded programming that can be avoided by developers are false sharing and poor data locality.

False Sharing

False sharing can cause some serious performance degradation on both dual- or multi-processor and HT-enabled systems. False sharing happens when multiple threads own private data on the same cache block. For Pentium 4 processors and Xeon processors, a cache block is effectively 128-bytes. Determining whether false sharing is an issue is easy with a profile from the VTune Analyzer, and fixing the problem is as easy as padding out data structures. Perhaps an even better fix is to structure data in a cache-friendly manner, on or at 128-byte boundaries. Note that these recommendations are very complimentary to those for avoiding 64K-aliasing, so watching out for one pitfall actually helps you prevent two or more! See item [5] in the Additional Resources section for a more in-depth explanation of false sharing.

The Cache Blocking Technique

The cache blocking technique restructures loops with frequent iterations over large data arrays by sub-dividing the large array into smaller blocks, or tiles. Each data element in the array is reused within the data block, such that the block of data fits within the data cache, before operating on the next block or tile. This technique is widely used in linear algebra, and is a common transformation applied by compilers and game programmers. Because HT-enabled processors share the L2 cache, the most effective target block size (or the sweet spot) is be somewhere around ~133KB per thread, or roughly a quarter of the full L2 cache size. See item [7] in the Additional Resources section for further details.

Write-Combining Store Buffers

Write-Combining Store Buffers are also a shared resource on HT-enabled systems. The Pentium 4 processor has six WC buffers, and in the past it has been recommended that programmers target four of the six, as the OS and other processes are likely consuming at least two. An example of targeting four WC buffers is writing to four addresses that fall on unique cache lines. With the WC buffers being shared, the recommendation for processors with HT technology is to only target two WC buffers per running thread. Again, the VTune Analyzer can help you determine whether WC buffer evictions are impacting performance. The solution to avoiding unwanted WC buffer evictions is to break apart a loop such that it only targets the recommended number of WC buffers.


Programming Tools
While you can keep an eye out for some issues and common pitfalls when developing code, you will find yourself debugging and/or fine-tuning some part of your game. Intel offers a full suite of tools to help you both reduce development time and increase your productivity.

  • Intel® C++ Compiler
  • The VTune™ Performance Analyzer
  • Intel® Thread Checker
  • Thread Profiler
  • Parallel Libraries
You can find out more about all these tools and how to effectively utilize them from http://www.intel.com/software/products/, http://developer.intel.com/ and http://www.intel.com/software.


Summary
In this exhaustive introduction we visited the models to achieve parallelism in your code, and discussed some of the common pitfalls and respective workarounds for developing threaded code for Hyper-Threading processors. We wrapped up our discussion with a very brief introduction to the software development tools provided by Intel. I encourage you to try out the tools right away and start experimenting with what is possible on today's advanced high-end desktop systems. Be aggressive with the application of the tools and their features; and profile often!

About the Author
Will Damon was a Technical Marketing Engineer within Intel's Software Solutions Group. He has a bachelor's degree in Computer Science from Virginia Polytechnic Institute and State University*, where he graduated with honors. He has been with Intel for over a year, helping game developers enable their titles to achieve the highest performance possible on Intel® Pentium® 4 processor-based PCs. He welcomes email regarding optimization, mathematics, physics, artificial intelligence, or anything else related to real-time 3D graphics, and gaming.


Additional Resources
4k aliasing对分块算法的影响和lapacke中行列主序的问题 由于程序运行时间测量的不准确性,虽然测量时间时已经采取了运行多次取中位值的方法,我不保证能够重现结果。下图是使用dgemm()矩阵乘法用时计算所得CPU浮点计算能力(Gflops,y轴,越大越好)随运行时间(x轴)变化的曲线。可见其波动是非常剧烈的,偶尔还会来个尖峰或者波谷。最底下的红线是笔记本低压U i7-8550U(外接电源),睿频结束后很快就稳定到110Gflops的位置。下图是AMD Th... 阅读详情

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内容概要:本文围绕Plecs平台构建的全桥LLC谐振变换器闭环仿真模型展开,系统阐述了基于变频与移相混合控制策略的设计与实现方法。模型深入剖析了LLC谐振变换器的工作机理,涵盖谐振腔关键参数设计、软开关实现条件、变频调制与移相控制的协同作用机制,并实现了完整的闭环控制系统仿真,能够有效验证变换器在不同负载与输入电压条件下的动态响应、效率表现及稳态性能。研究还整合了配套的参数设计资料与计算工具,支持从理论分析、参数设计到仿真验证的一体化开发流程,为高性能LLC变换器的研发提供了全面的技术支撑。; 适合人群:具备电力电子与电源变换基础知识的工程师、高校研究生,以及从事开关电源、DC-DC变换器研发的技术人员,特别适合需要掌握LLC谐振变换器建模、仿真与优化控制策略的科研与工程人员。; 使用场景及目标:①应用于LLC谐振变换器的科研教学与课程设计,深化对谐振工作模式、软开关机理及混合控制策略的理解;②作为实际产品研发中的仿真验证平台,用于优化控制算法、评估系统效率与动态性能;③支持对变频+移相协同控制、闭环稳定性、软开关范围拓展及最小化应力等关键技术进行深入研究与方案迭代。; 阅读建议:建议结合经典电力电子教材与LLC变换器专业设计手册进行学习,重点研读谐振参数设计与控制环路建模章节。实际应用时,应依据具体的硬件规格(如开关器件、磁性元件参数)精确调整仿真模型,并通过多轮仿真结果对比,不断优化系统设计方案。

半桥LLC谐振变换器开环+闭环仿真设计资料(Simulink仿真实现)

内容概要:本文档系统性地介绍了半桥LLC谐振变换器的开环与闭环仿真设计方法,基于Simulink平台构建完整的仿真模型,涵盖系统建模、关键参数设计、控制策略实现及动态性能验证全过程。重点阐述了LLC谐振变换器的工作原理、谐振腔参数(Lr、Cr、Lm)的优化设计方法、零电压开关(ZVS)与零电流开关(ZCS)等软开关技术的实现机制,并深入探讨电压/电流双闭环控制策略,特别是恒压恒流双竞争控制逻辑的切换机制与稳定性保障。资料配套提供完整的仿真模型、详细说明文档及参考文献,有助于全面掌握其在启停过程、负载突变等工况下的动态响应特性与系统鲁棒性调控方法。; 适合人群:具备电力电子技术基础理论知识和Simulink仿真操作能力的高校研究生、科研机构研究人员,以及从事高频高效开关电源、新能源汽车车载充电机(OBC)、充电桩电源、数据中心供电等领域的工程技术人员。; 使用场景及目标:① 掌握LLC谐振变换器在实际工程中的精确建模与仿真分析流程;② 深入理解并独立实现从开环频率调制到闭环反馈控制的平滑切换逻辑;③ 应用于高效率DC-DC变换器、电动汽车充电系统、可再生能源并网电源等场景下的控制系统设计与性能优化; 阅读建议:建议结合所提供的仿真模型进行分步调试与参数扫描实验,重点关注控制器带宽设计、谐振元件参数匹配对效率的影响以及系统上电过程中的软启动策略设计,同时推荐对比学习全桥LLC、CLLC等衍生拓扑的相关资料,以建立完整的谐振变换器控制体系认知。

SOP 配电网故障重构方法研究【IEEE33节点】(Matlab代码实现)

内容概要:本文围绕基于SOP(Soft Open Point)的配电网故障重构方法展开研究,采用IEEE33节点标准配电系统作为仿真测试平台,利用Matlab进行代码实现与仿真验证。研究重点在于通过SOP这一柔性电力电子装置实现故障后网络拓扑的快速重构,提升供电恢复能力与系统可靠性。文中详细阐述了故障重构的数学建模过程,结合优化算法实现负荷转供与孤岛划分的协同决策,在保证辐射状运行约束的前提下,最大限度恢复失电负荷,并降低网络损耗。该方法充分体现了SOP在主动配电网中的灵活调控优势,为现代智能配电网的自愈控制提供了有效技术路径。; 适合人群:电气工程及相关专业的高校研究生、从事配电网自动化与智能电网研究的科研人员,以及具备一定Matlab编程基础和电力系统分析背景的研发技术人员。; 使用场景及目标:① 掌握基于SOP的配电网故障恢复机制与重构策略设计;② 学习如何在Matlab环境下构建IEEE33节点系统模型并实现故障重构算法;③ 深入理解含分布式电源与柔性装置的主动配电网优化运行方法; 阅读建议:建议结合电力系统分析基础知识,重点关注SOP的建模方式、故障重构的优化目标与约束条件设定,并动手实践Matlab代码以加深对算法流程和仿真结果的理解。

双向全桥CLLC拓扑变频控制仿真模型(Simulink仿真实现)

内容概要:本文详细介绍了一套基于Simulink的双向全桥CLLC拓扑变频控制仿真模型,重点实现双闭环PWM控制策略下的谐振变换器系统仿真。该模型融合变频控制与移相控制技术,具备高频软开关特性,适用于电动汽车V2G充放电、高效DC-DC能量转换等高效率电力电子应用场景。资源涵盖闭环控制系统设计、关键参数整定方法、动态响应分析及完整的仿真验证流程,并提供配套PPT说明与参考文献,帮助深入理解控制逻辑与工程实现细节。此外,资源包还集成多种LLC、CLLC及PFC拓扑的仿真案例,具有较强的系统扩展性与科研参考价值,支持拓扑复用、控制算法迭代与多工况验证。; 适合人群:具备电力电子、自动控制理论基础,从事新能源、电动汽车、电源系统等领域研究的研究生、科研人员及电气工程师;熟悉Matlab/Simulink仿真环境者尤佳。; 使用场景及目标:①深入学习CLLC谐振变换器的工作机理与变频调制策略;②支撑科研项目中的拓扑选型、控制算法开发与系统级仿真验证;③用于毕业设计、学术论文复现或工业级电源产品的前期技术预研。; 阅读建议:建议结合文档中提供的多个仿真模型进行对比分析,重点关注双闭环结构(电压外环+电流内环)的设计原理与稳定性优化,同时利用配套资料系统掌握参数设计方法、谐振腔建模技巧及系统动态性能评估手段。

一份外盘期货历史高频tick数据,涵盖能源、贵金属、股指等主要品种的逐笔成交与盘口快照 每条记录包含精确至毫秒的时间戳、合约代码、成交价格、成交量以及主动买卖方向标识 同时提供该时刻的最优申买价、申卖

一份外盘期货历史高频tick数据,涵盖能源、贵金属、股指等主要品种的逐笔成交与盘口快照。每条记录包含精确至毫秒的时间戳、合约代码、成交价格、成交量以及主动买卖方向标识。同时提供该时刻的最优申买价、申卖价及对应挂单量,用于还原盘口深度变化,数据时间覆盖连续的多个交易日。 数据源:CMES金融数据库

高校技术转移办公室人员如何提升技术成果的市场化转化效率?.docx

科易网基于AI模型+行业大数据,在技术转移、成果转化、技术经纪、知识产权、产业创新、科技招商等垂直领域的多样化应用场景,推出科技创新领域的AI+工具与数智化解决方案,推动科技创新与产业创新智能化发展。

基于变频控制的多相交错LLC谐振变换器闭环仿真(Simulink仿真实现)

内容概要:本文档聚焦于电力电子与控制系统领域的仿真研究,核心内容为“基于变频控制的多相交错LLC谐振变换器闭环仿真”的Simulink实现。系统阐述了LLC谐振变换器的开环与闭环控制策略、软开关技术、恒压恒流双竞争控制机制、多相交错结构设计及变频调制原理,通过建模仿真深入剖析高频DC-DC变换器的工作特性与动态响应。文档整合了丰富的科研资源,涵盖双向CLLC、DAB变换器、PWM整流器、微电网优化调度、状态估计(EKF/UKF/PF)等多个前沿方向的仿真案例,形成一个体系完整、技术覆盖面广的综合性技术资料库,适用于高水平科研与工程实践。; 适合人群:电气工程、自动化、电力电子及相关专业的研究生、高校科研人员,以及从事新能源发电、电动汽车、智能电网、工业电源等领域的技术研发工程师。; 使用场景及目标:①开展高频谐振变换器拓扑结构与先进控制策略的深入研究;②完成复杂电力电子系统的建模、仿真与性能验证;③支撑SCI/EI论文撰写、科研项目申报与关键技术攻关;④辅助高校课程设计、研究生课题实践与毕业设计的仿真实验环节。; 阅读建议:建议结合文中提供的网盘资源与微信公众号资料进行系统学习,优先掌握LLC变换器的基本工作模态与谐振原理,再逐步深入闭环控制器设计与参数整定,仿真过程中应重点关注关键波形分析与系统稳定性判据,以全面提升对高频变换器动态特性的理解与工程应用能力。

产业园区运营负责人如何助力园区内企业与高校科研成果高效对接?.docx

科易网基于AI模型+行业大数据,在技术转移、成果转化、技术经纪、知识产权、产业创新、科技招商等垂直领域的多样化应用场景,推出科技创新领域的AI+工具与数智化解决方案,推动科技创新与产业创新智能化发展。

【多无人机追捕-逃逸】平面中多追捕者保证实现的分散式追捕-逃逸策略研究(Matlab代码实现)

内容概要:本文针对平面中多追捕者与逃逸者之间的对抗问题,提出了一种保证实现的分散式追捕-逃逸策略,并通过Matlab代码实现了完整的仿真验证。该策略面向多无人机系统在追捕任务中的协同控制需求,采用分散式架构设计,提升了系统的鲁棒性、可扩展性与任务适应能力。研究内容涵盖追捕与逃逸双方的动力学建模、策略设计原理、协同控制机制以及捕获条件的收敛性分析,重点解决了多智能体在无中心协调下的自主决策与协同围捕难题。通过多组仿真实验,验证了该策略在不同初始分布、障碍环境及动态扰动下的有效性与稳定性,展示了其在复杂场景中的优越性能。; 适合人群:具备控制理论、多智能体系统、博弈论或机器人路径规划基础知识,从事无人机协同控制、智能博弈、自主系统决策等相关方向研究的科研人员、高校研究生及自动化、电子信息类专业的高年级本科生。; 使用场景及目标:①应用于多无人机协同围捕、边境安防、目标监控与应急搜救等实际任务场景;②为多智能体系统中的分布式决策、非合作博弈与协同控制算法设计提供理论依据与代码实现参考;③帮助研究人员深入理解分散式控制在动态对抗环境中的实现机制、收敛条件与性能边界。; 阅读建议:建议结合提供的Matlab代码进行仿真实践,逐步调试并观察不同参数设置下的追捕效果,深入理解策略的实现细节;可进一步拓展至三维空间、非完整约束动力学模型或多目标逃逸等更复杂场景,以提升算法的实用性与泛化能力。

【顶级EI复现】基于KKT条件与分段解析优化的双有源桥DC-DC变换器软开关协同最小应力闭环控制方法(Simulink仿真实现)

内容概要:本文详细介绍了一种基于KKT条件与分段解析优化的双有源桥DC-DC变换器软开关协同最小应力闭环控制方法,属于高端电力电子系统控制领域的“顶级EI复现”级别研究。该方法融合最优控制理论与工程实践,通过构建精确的数学模型,在Simulink环境中实现了闭环仿真,有效解决了软开关实现过程中器件电压/电流应力过大的问题,达成了高效率与低损耗的协同优化目标。研究成果可广泛应用于新能源汽车、智能电网、工业电源等对功率密度和可靠性要求极高的电力转换场景。; 适合人群:面向具备电力电子、自动控制或电气工程等相关专业背景,从事科研仿真工作的硕士、博士研究生及高校科研人员,尤其适合熟悉双有源桥(DAB)拓扑结构、掌握Simulink建模技能,并具有优化控制与非线性系统分析基础的研发人员。; 使用场景及目标:①复现高水平EI期刊论文中的先进控制算法,提升科研竞争力;②深入理解KKT条件在电力电子实时优化控制中的数学机制与物理意义;③掌握DAB变换器中软开关与器件应力最小化的协同设计方法;④为撰写学术论文、开展课题研究或工程原型开发提供可运行的仿真模型与完整的技术路线支撑。; 阅读建议:建议结合文中提到的“顶级EI复现”背景,系统学习KKT最优性条件的推导过程及其在约束优化问题中的应用逻辑,并在Simulink中动手调试仿真模型,重点关注分段解析控制策略的实现细节与参数整定方法。推荐访问所提供的资源链接,获取YALMIP工具包及相关代码资料,以提高复现效率与研究深度。

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