vcs option +udpsched in gate level simulation without delay

When the udpsched switch is used, VCS treats the event to update the output of a sequential udp as if it was using a non-blocking assignment. This matches the scheduling of non-blocking assignments within the RTL code, and avoids any inconsistency of the scheduling of assignments.

 

Consider this simple example:

 

module test(input clk,rst, output reg x,y);

   always @(posedge clk, negedge rst) if (!rst) x <= 0; else x <= y;

   always @(posedge clk,negedge rst) if (!rst) y <= 1; y <= x; endmodule

 

After the reset condition, x is 0 and y is 1. In every clock cycle thereafter, the values of x and y are swapped.

According to the Verilog non-blocking behavior, the RHS