FPGA linux synplify综合工程的环境搭建

1、新建filelist.v文件，将需要综合的所有RTL代码include进去。

filelist.v文件如下：

`include "../../../lib/fpga/io/pad_cell_tsmc28.v"
`include "../../../lib/fpga/std/std_cell_tsmc28.v"
`include "相对路径/*****.v"                                    //其它文件

2、新建fdc约束文件，实现对fpga芯片中的管脚、时钟、复位信号进行约束，对时钟的周期、频率、占空比进行预定义。

约束文件top.fdc内容如下：

#创建时钟，CIN为外部时钟引脚，与晶振直接相连，假设本工程中外接50M晶振，其周期为20ns,占空比为50%
create_clock  -name {CIN} {p:CIN} -period {20} -waveform {0 10.0}
create_clock  -name {CLK_OUT1} {n:u_pll_fpga.CLK_OUT1} -period {10}
create_clock  -name {CLK_OUT2} {n:u_config.u_module_clk.CLK_OUT2} -period {5}

#将异步时钟约束为时钟组，作约束忽略
set_clock_groups -derive -asynchronous -name {clkgrp_CLK_OUT1} -group { {c:CLK_OUT1} }
set_clock_groups -derive -asynchronous -name {clkgrp_CLK_OUT2} -group { {c:CLK_OUT2} }
#复位信号约束
set_false_path -from {p:RSTN}

 

3、新建.tcl 脚本，实现建立完整的synplify工程

synplify.tcl文件内容如下：

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.8

#create a new project
project -new top.prj         #工程名命名为top

#add_file options
add_file -verilog "filelist.v"
add_file -fpga_constraint "top.fdc"

#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options,本设计中使用的xilinx的K7系列
set_option -technology Kintex7
set_option -part XC7K410T
set_option -package FFG900
set_option -speed_grade -2L
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 1
set_option -top_module "hello"  #顶层模块

#map options
set_option -frequency 50.000000  #外部晶振
set_option -auto_constrain_io 1
set_option -resolve_multiple_driver 1
set_option -srs_instrumentation 1
set_option -RWCheckOnRam 0
set_option -run_prop_extract 0
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -retiming 1
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -enable_prepacking 1
set_option -use_vivado 1         #指定布局布线的工具，本设计中指定vivado

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 10
set_option -num_startend_points 10
set_option -project_relative_includes 1
set_option -hdl_define -set FPGA

set_option -include_path "./hdl/"    #设置源码路径

#simulation options
set_option -write_verilog 1
set_option -write_vhdl 0

#VIF options
set_option -write_vif 0

#set result format/file last
project -result_file "top.edf"
project -log_file "top.log"

#save run and close project
project -save top.prj
project -run
project -close top.prj

4、新建makefile文件

SYNPLIFY_DIR = synplify
SYNPLIFY_TCL_FILE = synplify.tcl
SYNPLIFY_FDC_FILE = top.fdc
SYNPLIFY_VERILOG_FILE = filelist.v
SYNPLIFY_EDF_FILE = top.edf      #综合后的网表文件edf格式
SYNPLIFY_LOG_FILE = top.log
SYNPLIFY_VM_FILE = hello.vm      #综合后的网表文件vm格式，可作后仿真的输入



.PHONY:  run_synplify clean

run_synplify:
	echo "synthesize begin ..."
	rm -rf ${SYNPLIFY_DIR}
	mkdir ${SYNPLIFY_DIR}
	cd ${SYNPLIFY_DIR} && synplify_pro -batch synplify.tcl
	cp ${SYNPLIFY_DIR}/rev_1/*.edf ./${SYNPLIFY_EDF_FILE}
	cp ${SYNPLIFY_DIR}/rev_1/*.vm ./${SYNPLIFY_VM_FILE}
	cp ${SYNPLIFY_DIR}/top.log ./${SYNPLIFY_LOG_FILE}
	echo "synthesize finished!"


clean:
	rm -rf ${SYNPLIFY_DIR}
	rm -rf ./${SYNPLIFY_EDF_FILE}
	rm -rf ./${SYNPLIFY_LOG_FILE}
	rm -rf ./${SYNPLIFY_VM_FILE}
	

5、执行makefile

当前路径下输入指令 make run_synplify ，等待完成。

6、查看top.log文件，可查看该型号fpga综合后的时钟，资源使用率等信息