<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[membre_non的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/membre_non</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; membre_non]]></copyright><item><title><![CDATA[【实用】将优快云公开文章保存为PDF的方法]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/141994346</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/141994346</guid><author>membre_non</author><pubDate>Sat, 07 Sep 2024 13:14:59 +0800</pubDate><description><![CDATA[在弹出页面内选择“边距”->“最小”，显示完整文章内容界面，保存即可。打开开发者模式，并切换到控制台（Console）。粘贴以下片段，回车。]]></description><category></category></item><item><title><![CDATA[PCIe学习笔记3：PCIe配置——PCIe拓扑与配置地址空间]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/139069552</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/139069552</guid><author>membre_non</author><pubDate>Tue, 21 May 2024 16:05:44 +0800</pubDate><description><![CDATA[PCI Express（PCIe）学习笔记]]></description><category></category></item><item><title><![CDATA[PCIe学习笔记2：PCIe体系架构——PCIe设备层次]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/139029284</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/139029284</guid><author>membre_non</author><pubDate>Sun, 19 May 2024 16:51:32 +0800</pubDate><description><![CDATA[PCI Express（PCIe）学习笔记]]></description><category></category></item><item><title><![CDATA[PCIe学习笔记1：PCIe体系架构——PCIe简介]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/139010399</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/139010399</guid><author>membre_non</author><pubDate>Sat, 18 May 2024 16:40:50 +0800</pubDate><description><![CDATA[PCI Express（PCIe）学习笔记]]></description><category></category></item><item><title><![CDATA[Vitis/Vivado HLS 流水线中的存储依赖——解决方法之二]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/139004236</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/139004236</guid><author>membre_non</author><pubDate>Fri, 17 May 2024 15:19:49 +0800</pubDate><description><![CDATA[利用寄存器避免HLS流水线中的存储依赖]]></description><category></category></item><item><title><![CDATA[Verilog 利用握手信号（valid/ready）实现数据流水线反压]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/138471947</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/138471947</guid><author>membre_non</author><pubDate>Sun, 05 May 2024 19:32:50 +0800</pubDate><description><![CDATA[通过握手信号实现数据流水线的反压]]></description><category></category></item><item><title><![CDATA[Verilog/SystemVerilog 1位全加器实现32位全加器 - Module fadd]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/137994765</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/137994765</guid><author>membre_non</author><pubDate>Sat, 20 Apr 2024 11:43:27 +0800</pubDate><description><![CDATA[HDLBits 练习 Module fadd]]></description><category></category></item><item><title><![CDATA[Verilog FIFO转AXI4-Full模块的RTL简单实现 - Master主机]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/137968921</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/137968921</guid><author>membre_non</author><pubDate>Fri, 19 Apr 2024 16:15:07 +0800</pubDate><description><![CDATA[FIFO转AXI4-Full主机模块]]></description><category></category></item><item><title><![CDATA[Vitis/Vivado HLS 利用ROM实现简易正弦波发生器]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/137787705</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/137787705</guid><author>membre_non</author><pubDate>Mon, 15 Apr 2024 17:32:36 +0800</pubDate><description><![CDATA[HLS自动实现ROM推断，模块完成正弦波形发生]]></description><category></category></item><item><title><![CDATA[Vitis/Vivado HLS 流水线中的存储依赖——解决方法之一]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/137506911</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/137506911</guid><author>membre_non</author><pubDate>Mon, 08 Apr 2024 14:46:41 +0800</pubDate><description><![CDATA[通过增加循环空转，解决流水线中存储依赖的问题]]></description><category></category></item><item><title><![CDATA[Vitis/Vivado HLS 纯数据流驱动流水线pipeline的IP核构建]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/137452270</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/137452270</guid><author>membre_non</author><pubDate>Sun, 07 Apr 2024 09:55:42 +0800</pubDate><description><![CDATA[高层次综合HLS代码风格分享]]></description><category></category></item><item><title><![CDATA[【VCS】VCS报错：/libvcsnew.so: undefined reference to ‘xxx‘]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/134406829</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/134406829</guid><author>membre_non</author><pubDate>Tue, 14 Nov 2023 20:02:35 +0800</pubDate><description><![CDATA[【代码】【VCS】VCS报错：/libvcsnew.so: undefined reference to ‘xxx‘]]></description><category></category></item><item><title><![CDATA[Vivado XSIM仿真器 前仿真、后仿真寄存器信号输出高阻态]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/131725992</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/131725992</guid><author>membre_non</author><pubDate>Fri, 14 Jul 2023 16:17:26 +0800</pubDate><description><![CDATA[因为计数器从8192倒序计数到0，综合后寄存器被优化为了14位。在综合后、布线后的行为仿真和时序仿真都显示高阻Z，且复位信号不起作用。因为解决不了modelsim综合后仿真一直报错的问题，只能先用Vivado自带的XSIM仿真，遇到了一个莫名其妙的bug。综合后仿真波形正常。在模块中定义了20位的计数器。]]></description><category></category></item><item><title><![CDATA[Vitis HLS C/RTL Cosim 报错 “Failed to compile generated C file xsim.dir/diamond/obj/xsim_2.c。”]]></title><link>https://blog.youkuaiyun.com/membre_non/article/details/128414894</link><guid>https://blog.youkuaiyun.com/membre_non/article/details/128414894</guid><author>membre_non</author><pubDate>Thu, 22 Dec 2022 23:36:47 +0800</pubDate><description><![CDATA[Vitis HLS C/RTL Cosim 报错 “Failed to compile generated C file 
 sim.dir/diamond/obj/xsim_2.c。”]]></description><category></category></item></channel></rss>