博主记录了每日的工作进展，包括对top_bench.vin的ModelSimSE6.5b仿真，初步观察信号、块和架构；以及深入研究神经模糊逻辑混合信号处理器和RBFNN，发现了一个16位RISC作为学习RISC实现的起点。
Update records for everyday
09/01/2013:
Ran the simulation of top_bench.v in ModelSim SE 6.5b with RILL's code: E:\or1200-1.35\sim\rtl_sim\modelsim_sim, and got the 1st glimpse on the signal, blocks and architecture.
08/31/2013:
Went through the Neuro-Fuzzy logic mixed signal processor and plan to follow RBFNN (2013 ISCAS).
And found there is a 16bit RISC in the digital controller so recalled the OpenRISC1200 as a good start point to learn RISC implementation on DE2 with different free soft-core IPs ( Xiang Li's 2011 MSEE thesis: they used 4 other IP: CONMAX IP Core; Memory Controller IP Core; UART16550 IP Core; GPIO IP Core)
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