40bit位宽使用

 40-bit Register Usage
The ALU registers of the SHARC processors are 40 bits in width in order
to support the 40-bit extended precision floating-point mode. However,
the C/C++ run-time environment does not support this mode and,
instead, runs with 32-bit rounding enabled (bit RND32=1 in the MODE1 reg-
ister). The eight additional Least Significant Bits (LSBs) of the mantissa
are, therefore, not used in C/C++ applications. 40-bit computations can
only be performed in assembly code. The RND32 bit should be explicitly
cleared and set around the computation code.

40bit的扩展模式只是在汇编下支持，所以要想在C环境使用40bit扩展精度的计算是

不可能的，同时，在使用汇编写40bit扩展运算的时候， RND32要确保是置0.

VDK preserves the 40-bit form of the data registers during a context
switch (but only when the RND32 bit is cleared to indicate that 40-bit arith-
metic is enabled). Additionally, the VDK Timer ISR protects against
overwriting the 40-bit data registers by running in the alternate register
set