s5pv210 spi 配置 ---可参考S3C6410篇

本文详细介绍了S3C6410 SPI控制器的初始化步骤、全双工收发协议分析以及SPI收发条件判断,包括如何设置SPI模块、配置参数、发送和接收数据流程以及状态寄存器的判断方法。

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S3C6410 SPI全双工读写流程分析

一、SPI控制器datasheet

1详细请参考:http://blog.youkuaiyun.com/hustyangju/article/details/20474659

2 SPI的所有寄存器都是映射到内核空间的,采用基地址+偏移地址的方式访问

static volatile void  __iomem *spiregs;                            //global variable for mapping spiregister

spiregs = (volatile)ioremap(0x7F00B000,0x30);  //just request for the spi0

3 下文可能用到的偏移地址

 

  1. #define S3C_CH_CFG                (0x00)     //SPI configuration  
  2. #define S3C_CLK_CFG               (0x04)      //Clock configuration  
  3. #define S3C_MODE_CFG                   (0x08)     //SPI FIFO control  
  4. #define S3C_SLAVE_SEL            (0x0C)      //Slave selection  
  5. #define S3C_SPI_INT_EN                   (0x10)      //SPI interrupt enable  
  6. #define S3C_SPI_STATUS          (0x14)      //SPI status  
  7. #define S3C_SPI_TX_DATA                (0x18)      //SPI TX data  
  8. #define S3C_SPI_RX_DATA                (0x1C)      //SPI RX data  
  9. #define S3C_PACKET_CNT                (0x20)      //count how many data master gets  
  10. #define S3C_PENDING_CLR             (0x24)      //Pending clear  
  11. #define S3C_SWAP_CFG           (0x28)      //SWAPconfig register  
  12. #define S3C_FB_CLK                  (0x28)     //SWAP FB config register  
  13.    
  14.    
  15. #define SPI_CH_SW_RST                   (1<<5)  
  16. #define SPI_CH_MASTER                  (0<<4)  
  17. #define SPI_CH_SLAVE              (1<<4)  
  18. #define SPI_CH_RISING            (0<<3)  
  19. #define SPI_CH_FALLING                   (1<<3)  
  20. #define SPI_CH_FORMAT_A             (0<<2)  
  21. #define SPI_CH_FORMAT_B             (1<<2)  
  22. #define SPI_CH_RXCH_OFF              (0<<1)  
  23. #define SPI_CH_RXCH_ON               (1<<1)  
  24. #define SPI_CH_TXCH_OFF               (0<<0)  
  25. #define SPI_CH_TXCH_ON                (1<<0)  
  26.    
  27. #define SPI_CLKSEL_PCLK                 (0<<9)  
  28. #define SPI_CLKSEL_USBCLK   (1<<9)  
  29. #define SPI_CLKSEL_ECLK                 (2<<9)  
  30. #define SPI_ENCLK_DISABLE  (0<<8)  
  31. #define SPI_ENCLK_ENABLE   (1<<8)  
  32.    
  33. #define SPI_MODE_CH_TSZ_BYTE (0<<29)  
  34. #define SPI_MODE_CH_TSZ_HALFWORD       (1<<29)  
  35. #define SPI_MODE_CH_TSZ_WORD       (2<<29)  
  36. #define SPI_MODE_BUS_TSZ_BYTE        (0<<17)  
  37. #define SPI_MODE_BUS_TSZ_HALFWORD     (1<<17)  
  38. #define SPI_MODE_BUS_TSZ_WORD     (2<<17)  
  39. #define SPI_MODE_RXDMA_OFF    (0<<2)  
  40. #define SPI_MODE_RXDMA_ON     (1<<2)  
  41. #define SPI_MODE_TXDMA_OFF    (0<<1)  
  42. #define SPI_MODE_TXDMA_ON     (1<<1)  
  43. #define SPI_MODE_SINGLE              (0<<0)  
  44. #define SPI_MODE_4BURST             (1<<0)  
  45.    
  46. #define SPI_SLAVE_MAN                   (0<<1)  
  47. #define SPI_SLAVE_AUTO                  (1<<1)  
  48. #define SPI_SLAVE_SIG_ACT   (0<<0)  
  49. #define SPI_SLAVE_SIG_INACT        (1<<0)  
  50.    
  51. #define SPI_INT_TRAILING_DIS      (0<<6)  
  52. #define SPI_INT_TRAILING_EN       (1<<6)  
  53. #define SPI_INT_RX_OVERRUN_DIS       (0<<5)  
  54. #define SPI_INT_RX_OVERRUN_EN        (1<<5)  
  55. #define SPI_INT_RX_UNDERRUN_DIS    (0<<4)  
  56. #define SPI_INT_RX_UNDERRUN_EN     (1<<4)  
  57. #define SPI_INT_TX_OVERRUN_DIS        (0<<3)  
  58. #define SPI_INT_TX_OVERRUN_EN         (1<<3)  
  59. #define SPI_INT_TX_UNDERRUN_DIS    (0<<2)  
  60. #define SPI_INT_TX_UNDERRUN_EN     (1<<2)  
  61. #define SPI_INT_RX_FIFORDY_DIS (0<<1)  
  62. #define SPI_INT_RX_FIFORDY_EN  (1<<1)  
  63. #define SPI_INT_TX_FIFORDY_DIS (0<<0)  
  64. #define SPI_INT_TX_FIFORDY_EN  (1<<0)  
  65.    
  66. #define SPI_STUS_TX_DONE   (1<<21)  
  67. #define SPI_STUS_TRAILCNT_ZERO        (1<<20)  
  68. #define SPI_STUS_RX_OVERRUN_ERR   (1<<5)  
  69. #define SPI_STUS_RX_UNDERRUN_ERR         (1<<4)  
  70. #define SPI_STUS_TX_OVERRUN_ERR    (1<<3)  
  71. #define SPI_STUS_TX_UNDERRUN_ERR          (1<<2)  
  72. #define SPI_STUS_RX_FIFORDY       (1<<1)  
  73. #define SPI_STUS_TX_FIFORDY       (1<<0)  
  74.    
  75. #define SPI_PACKET_CNT_DIS         (0<<16)  
  76. #define SPI_PACKET_CNT_EN (1<<16)  


二、重点参数及初始化步骤


1 双通道SPI管脚配置



2 传输模型配置

/*     Set transfer type (CPOL & CPHA set)    */

         spi_chcfg= SPI_CH_RISING | SPI_CH_FORMAT_A;

         spi_chcfg|= SPI_CH_MASTER;

         writel(spi_chcfg , spiregs + S3C_CH_CFG);

详细请参考:http://blog.youkuaiyun.com/hustyangju/article/details/20474659

3 时钟配置


使用PCLK,外部时钟66M,100分屏:

 

/*     Set clock configuration register    

        *       SPIclockout = clock source / (2 * (prescaler +1))    

         *       PCLK=66Mhz, SPI clockout = clock source /(2 * (prescaler +1))      */

         spi_clkcfg= SPI_ENCLK_ENABLE;

         spi_clkcfg|= SPI_CLKSEL_PCLK;

         writel(spi_clkcfg , spiregs + S3C_CLK_CFG);

         spi_clkcfg= readl( spiregs + S3C_CLK_CFG);

 

         spi_clkcfg|= 49;       // the least spi speed =660Khz

         writel(spi_clkcfg , spiregs + S3C_CLK_CFG);

4 SPI 模块设置


/*     Set SPI MODE configuration register    */

         spi_modecfg= SPI_MODE_CH_TSZ_BYTE| SPI_MODE_BUS_TSZ_BYTE;

         spi_modecfg|= SPI_MODE_TXDMA_OFF| SPI_MODE_SINGLE| SPI_MODE_RXDMA_OFF;

         spi_modecfg&= ~( 0x3f << 5);

         spi_modecfg|= ( 0x1 << 5);    // Tx FIFOtrigger level in INT mode

         spi_modecfg&= ~( 0x3f << 11);

         spi_modecfg|= ( 0x1 << 11);           // Rx FIFOtrigger level in INT mode

         spi_modecfg&= ~( 0x3ff << 19);     

         spi_modecfg|= ( 0x1 << 19);   // Counting ofTailing Bytes

 

         writel(spi_modecfg,spiregs + S3C_MODE_CFG);

 

设置在fifo和bus中的数据宽度为byte,关闭DMA访问fifo,并设置fifo中保存最大字节数为1,设置接收和发送fifo的触发值为1byte。

5 中断配置


/*     SetSPI INT_EN register   */

         writel(spi_inten,spiregs + S3C_SPI_INT_EN); //u32 spi_inten =0x00

         writel(0x1f,spiregs + S3C_PENDING_CLR);

6 设置最大接收数据包数量

SPI can control the number of packets to bereceived in master mode. If there is any number of packets to bereceived, justset the SFR (Packet_Count_reg). SPI stops generating SPICLK when the number ofpackets is thesame as what you set. It is mandatory to follow software orhardware reset before this function is reloaded.(Software reset can clear allregisters except special function registers, but hardware reset clears allregisters.)

这里使能并设置为最大值。

/*     Set Packet Count configuration register        */

         spi_packet= SPI_PACKET_CNT_EN;

         spi_packet|= 0xffff;

writel(spi_packet,spiregs + S3C_PACKET_CNT);


7 打开spi接收和发送通道

/*     SetTx or Rx Channel on   */

         spi_chcfg= readl(spiregs + S3C_CH_CFG);

         spi_chcfg|= SPI_CH_TXCH_OFF | SPI_CH_RXCH_OFF;

         spi_chcfg|= SPI_CH_TXCH_ON;

         spi_chcfg|= SPI_CH_RXCH_ON;

         writel(spi_chcfg,spiregs + S3C_CH_CFG);

8 启动发送/接收和关闭送法/接收


通过置0和置1NSSOUT位来开启和关闭。

三 SPI全双工收发协议分析

1 全双工,就是TX和RX同时进行。

2 往哪里收?往哪里发?


datasheet上:CPU (or DMA) mustwrite data on the register SPI_TX_DATA, to write data in FIFO. Data on theregister areautomatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU (orDMA) must access the registerSPI_RX_DATA and then data are automatically sentto the register SPI_RX_DATA.

所以,对于处在内核空间的驱动来说,发送数据是往SPI_TX_DATA寄存器里写数据,接收是往SPI_RX_DATA寄存器里读数据。当然没这么简单!!

3 SPI发数据流程分析

提醒一点:SPI支持全双工,注意外设是半双工还是全双工?

按照上文设置,我们每次发送和接收一个byte。

(1)置0 NSSOUT

(2)往SPI_TX_DATA寄存器写一个byte,byte数据会自动移入TX FIFO,因为(1)中已经选中了外设,所以SPI master会自动读取TX FIFO中的byte数据移入TX移位寄存器,并开始发往bus。

(3)也就是说,驱动只需要从内核空间往SPI_TX_DATA寄存器上写数据,就完成了SPI发数据的操作了。

(4)全双工,意味着,发数据的同时也要从SPI_RX_DATA寄存器中读一个byte数据。但是,有可能第一次读并不会真正读到数据,因为没有数据被接收到RX移位寄存器。所以忽略这次的读取数据。

(5)置1 NSSOUT

4 SPI接收数据流程分析

如果外设是单双工,考虑在读数据的时候对spi复位!因为如果读数据发生在写数据后面,数据已经在发数据时读取到RX FIFO中了,只需从SPI_RX_DATA中取出数据就行了。

(1)置0 NSSOUT

(2)因为全双工,在发送数据的同时,spi master会读取byte字节并移入RX FIFO。所以从SPI_RX_DATA寄存器读取一个byte,byte数据会自动R从X FIFO移入到SPI_RX_DATA寄存器。(3)也就是说,驱动只需要从内核空间往SPI_RX_DATA寄存器读取数据,就完成了SPI接收数据的操作了。

(4)全双工,意味着,接收数据的同时也要从SPI_TX_DATA寄存器中发送一个byte数据。但是,读数据的时候发送的数据可能不是真正想要发送的数据,因为有些外设不是全双工工作。

(5)置1 NSSOUT

5 SPI收发条件判断

这是SPI收发协议里最难的部分了。

SPI状态寄存器:


1 是否准备好发数据?

  1. /*     spi_wait_TX_ready()- wait for TX_READY and TX_DONE       */  
  2. static BOOL spi_wait_TX_ready( void)  
  3. {  
  4.          unsignedlong loops = msecs_to_loops(10);  
  5.          u32val = 0;  
  6.          do{  
  7.                    val= readl(spiregs + S3C_SPI_STATUS);  
  8.          }while(!((val & SPI_STUS_TX_DONE) && (val & SPI_STUS_TX_FIFORDY))&& loops--);  
  9.           
  10.          if(loops == 0)  
  11.                    returnFALSE;  
  12.          else  
  13.                    returnTRUE;  
  14. }  


2 发数据是否完成?

  1. /*     spi_wait_TX_done()- wait for TX_DONE         */  
  2. static BOOL spi_wait_TX_done( void)  
  3. {  
  4.          unsignedlong loops = msecs_to_loops(10);  
  5.          u32val = 0;  
  6.          do{  
  7.                    val= readl(spiregs + S3C_SPI_STATUS);  
  8.          }while(!(val & SPI_STUS_TX_DONE)  &&loops--);  
  9.           
  10.          if(loops == 0)  
  11.                    returnFALSE;  
  12.          else  
  13.                    returnTRUE;  
  14. }  


3 是否准备好接收数据?

  1. /*     spi_wait_RX_ready()- wait for RX_READY      */  
  2. static BOOL spi_wait_RX_ready( void)  
  3. {  
  4.          unsignedlong loops = msecs_to_loops(10);  
  5.          u32val = 0;  
  6.          do{  
  7.                    val= readl(spiregs + S3C_SPI_STATUS);  
  8.          }while(!(val & SPI_STUS_TRAILCNT_ZERO) && loops--);  
  9.           
  10.          if(loops == 0)  
  11.                    returnFALSE;  
  12.          else  
  13.                    returnTRUE;  
  14. }  

6 最终全双工SPI从半双工外设发送和接收数据函数
  1. BOOL spi_sendbyte( BYTE data)  
  2. {  
  3.          BYTEchr;  
  4.          u32spi_chcfg = spiregs + S3C_CH_CFG;  
  5.    
  6.          if(!spi_wait_TX_ready())  
  7.          {  
  8.                    printk("%s:failed to get tx channel.\n");  
  9.                    returnFALSE;  
  10.          }  
  11.          writel(data, spiregs + S3C_SPI_TX_DATA);  
  12.          while(!spi_wait_RX_ready());  
  13.          readl(spiregs + S3C_SPI_RX_DATA);  
  14.          returnTRUE;  
  15. }  
  16.    
  17. /*     spi_flush_fifo()- Clear the TxFIFO , RxFIFO and TX/RX shift register 
  18.  *     @spiregs: the SPI register address*/  
  19. VOID spi_flush_fifo(void *spiregs)  
  20. {  
  21.          /*     soft rest the spi controller, flush theFIFO       */  
  22.          if(spi_wait_TX_done())  
  23.          {  
  24.                    writel(readl(spiregs+ S3C_CH_CFG) | SPI_CH_SW_RST, spiregs + S3C_CH_CFG);  
  25.                    writel(readl(spiregs+ S3C_CH_CFG) & ~SPI_CH_SW_RST, spiregs + S3C_CH_CFG);  
  26.          }  
  27. }  
  28.    
  29. /*     spi_readbyte()- Read a byte received on SPI0         */  
  30. BYTE spi_readbyte( void)  
  31. {  
  32.          u32tmp;  
  33.          u32spi_chcfg = spiregs + S3C_CH_CFG;  
  34.          BYTEret;  
  35.    
  36.          if(!spi_wait_TX_ready())  
  37.                    returnFALSE;  
  38.          spi_flush_fifo(spiregs);  
  39.          writel(0xFF, spiregs + S3C_SPI_TX_DATA);  
  40.           
  41.          if(spi_wait_RX_ready())  
  42.          {  
  43.                    tmp= readl(spiregs + S3C_SPI_RX_DATA);  
  44.                    ret= tmp & 0xff;  
  45.          }  
  46.          returnret;  
  47. }  
  48.           
ESP-ROM:esp32c3-api1-20210207 Build:Feb 7 2021 rst:0xc (RTC_SW_CPU_RST),boot:0xc (SPI_FAST_FLASH_BOOT) Saved PC:0x4038081c --- 0x4038081c: esp_restart_noos at D:/Espressif/frameworks/esp-idf-v5.3.3/components/esp_system/port/soc/esp32c3/system_internal.c:110 SPIWP:0xee mode:DIO, clock div:1 load:0x3fcd5820,len:0x1820 load:0x403cc710,len:0xbcc load:0x403ce710,len:0x2f5c entry 0x403cc71a I (35) boot: ESP-IDF v5.3.3-dirty 2nd stage bootloader I (35) boot: compile time Jun 24 2025 16:46:47 I (35) boot: chip revision: v0.3 I (39) boot: efuse block revision: v1.2 I (43) boot.esp32c3: SPI Speed : 80MHz I (48) boot.esp32c3: SPI Mode : DIO I (53) boot.esp32c3: SPI Flash Size : 2MB I (57) boot: Enabling RNG early entropy source... I (63) boot: Partition Table: I (66) boot: ## Label Usage Type ST Offset Length I (74) boot: 0 nvs WiFi data 01 02 00009000 00006000 I (81) boot: 1 phy_init RF data 01 01 0000f000 00001000 I (89) boot: 2 factory factory app 00 00 00010000 00177000 I (96) boot: End of partition table I (100) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0a1a4h ( 41380) map I (115) esp_image: segment 1: paddr=0001a1cc vaddr=3fc8dc00 size=0142ch ( 5164) load I (118) esp_image: segment 2: paddr=0001b600 vaddr=40380000 size=04a18h ( 18968) load I (129) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1c864h (116836) map I (153) esp_image: segment 4: paddr=0003c88c vaddr=40384a18 size=09048h ( 36936) load I (164) boot: Loaded app from partition at offset 0x10000 I (164) boot: Disabling RNG early entropy source... I (176) cpu_start: Unicore app I (184) cpu_start: Pro cpu start user code I (184) cpu_start: cpu freq: 160000000 Hz I (184) app_init: Application information: I (187) app_init: Project name: wifi_dongle I (192) app_init: App version: 1 I (197) app_init: Compile time: Jun 24 2025 16:48:19 I (203) app_init: ELF file SHA256: 9df487155... I (208) app_init: ESP-IDF: v5.3.3-dirty I (213) efuse_init: Min chip rev: v0.3 I (218) efuse_init: Max chip rev: v1.99 I (223) efuse_init: Chip rev: v0.3 I (228) heap_init: Initializing. RAM available for dynamic allocation: I (235) heap_init: At 3FC90140 len 0002FEC0 (191 KiB): RAM I (241) heap_init: At 3FCC0000 len 0001C710 (113 KiB): Retention RAM I (248) heap_init: At 3FCDC710 len 00002950 (10 KiB): Retention RAM I (255) heap_init: At 50000000 len 00001FE8 (7 KiB): RTCRAM I (262) spi_flash: detected chip: generic I (266) spi_flash: flash io: dio W (270) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header. I (283) sleep: Configure to isolate all GPIO pins in sleep state I (290) sleep: Enable automatic switching of GPIO sleep configuration I (297) main_task: Started on CPU0 I (307) main_task: Calling app_main() I (317) uart: queue free spaces: 20 Guru Meditation Error: Core 0 panic&#39;ed (Stack protection fault). Detected in task "Task" at 0x40386e32 --- 0x40386e32: rtos_int_exit_end at D:/Espressif/frameworks/esp-idf-v5.3.3/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S:726 Stack pointer: 0x3fc95f90 Stack bounds: 0x73756264 - 0x00000000 Core 0 register dump: MEPC : 0x403867a6 RA : 0x40386836 SP : 0x3fc95f90 GP : 0x3fc8e400 --- 0x403867a6: vPortClearInterruptMaskFromISR at D:/Espressif/frameworks/esp-idf-v5.3.3/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:529 --- 0x40386836: vPortExitCritical at D:/Espressif/frameworks/esp-idf-v5.3.3/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:641 TP : 0x3fc96080 T0 : 0x42004e70 T1 : 0x00000000 T2 : 0x00000000 --- 0x42004e70: esp_cleanup_r at D:/Espressif/frameworks/esp-idf-v5.3.3/components/newlib/newlib_init.c:43 S0/FP : 0x3fc8dd54 S1 : 0x0000000a A0 : 0x00000001 A1 : 0x00001400 A2 : 0x0000000a A3 : 0x60010000 A4 : 0x00000000 A5 : 0x600c2000 A6 : 0x3fc93568 A7 : 0x00000000 S2 : 0x00000008 S3 : 0x3fc8faa4 S4 : 0x00000000 S5 : 0x00000008 S6 : 0x000003f8 S7 : 0x00000000 S8 : 0x00000000 S9 : 0x00000000 S10 : 0x00000000 S11 : 0x00000000 T3 : 0x00000000 T4 : 0x00000000 T5 : 0x00000000 T6 : 0x00000000 MSTATUS : 0x00001881 MTVEC : 0x40380001 MCAUSE : 0x0000001b MTVAL : 0x00008082 --- 0x40380001: _vector_table at D:/Espressif/frameworks/esp-idf-v5.3.3/components/riscv/vectors_intc.S:54 MHARTID : 0x00000000 Stack memory: 3fc95f90: 0x00000008 0x00000008 0x00000001 0x420083d2 0x3fc90098 0x00000008 0x00000001 0x42008580 --- 0x420083d2: uart_enable_tx_intr at D:/Espressif/frameworks/esp-idf-v5.3.3/components/esp_driver_uart/src/uart.c:666 --- 0x42008580: uart_tx_all at D:/Espressif/frameworks/esp-idf-v5.3.3/components/esp_driver_uart/src/uart.c:1424 3fc95fb0: 0x00000000 0x00000000 0x00000008 0xc92b82db 0x00000000 0x00000000 0x00000000 0x00000000 3fc95fd0: 0x00000064 0x00000001 0x00000008 0x42009044 0x4038658e 0x00000000 0x00000000 0x4200aefe --- 0x42009044: uart_write_bytes at D:/Espressif/frameworks/esp-idf-v5.3.3/components/esp_driver_uart/src/uart.c:1467 --- 0x4038658e: vPortTaskWrapper at D:/Espressif/frameworks/esp-idf-v5.3.3/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:251 --- 0x4200aefe: safe_uart_write at D:/Espressif/User_Code/wifi_dongle/components/BSP/Modbus/Modbus.c:23 3fc95ff0: 0x3fc8faa4 0x00000006 0x3fc8faa0 0x4200afb8 0x00000000 0x00000000 0x3fc8faa0 0x4200b0dc --- 0x4200afb8: sendTxBuffer at D:/Espressif/User_Code/wifi_dongle/components/BSP/Modbus/Modbus.c:96 (discriminator 1) --- 0x4200b0dc: SendQueryToSlave at D:/Espressif/User_Code/wifi_dongle/components/BSP/Modbus/Modbus.c:181 3fc96010: 0x00000000 0x3fc8faa0 0x00000000 0x4200b202 0x00050304 0x00000001 0x00000000 0x00000000 --- 0x4200b202: modbus_master_task at D:/Espressif/User_Code/wifi_dongle/components/BSP/Modbus/Modbus.c:199 3fc96030: 0x00050304 0x00000001 0x00000000 0xc92b82db 0x00000000 0x00000000 0x00000000 0x4038659a --- 0x4038659a: vPortTaskWrapper at D:/Espressif/frameworks/esp-idf-v5.3.3/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:258 3fc96050: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc96070: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x00000150 0x3fc97140 3fc96090: 0x00000000 0x3fc95f10 0x3fc8f1fc 0x3fc971ec 0x3fc8f1f4 0x00000017 0x00000000 0x00000000 3fc960b0: 0x3fc971ec 0x00000000 0x00000002 0x3fc961e8 0x6f4d794d 0x73756264 0x6b736154 0x00000000 3fc960d0: 0x3fc971e0 0x00000002 0x00000000 0x00000000 0x00000001 0x00000000 0x3fc9092c 0x3fc90994 3fc960f0: 0x3fc909fc 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x42004e70 --- 0x42004e70: esp_cleanup_r at D:/Espressif/frameworks/esp-idf-v5.3.3/components/newlib/newlib_init.c:43 3fc96110: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc96130: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc96150: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc96170: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc96190: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc961b0: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 3fc961d0: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001000 0xa5a5a5a5 0xa5a5a5a5 3fc961f0: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96210: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96230: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96250: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96270: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96290: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc962b0: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc962d0: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc962f0: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96310: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96330: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96350: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 3fc96370: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 ELF file SHA256: 9df487155
最新发布
06-25
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