利用cpld对ads8556控制

最新推荐文章于 2017-10-06 23:05:04 发布

原创最新推荐文章于 2017-10-06 23:05:04 发布 · 1.1k 阅读

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#cpld #ads8556 #时序

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该博客介绍了如何利用CPLD器件来控制ADS8556模数转换器的工作时序。通过FSM_8556模块，详细描述了状态机的实现，包括对CONVST、CS、RD信号的控制，以及50kHz时钟的生成。内容涵盖了计数器、状态切换和信号同步等关键步骤。

module FSM_8556(clk_5k,clk_50,reset,convst,rd,cs,busy,rst,adc_stby,adc_range,
adc_word,adc_par, adc_hw,adc_wr);
input clk_5k,busy,rst;
output convst,cs,rd,reset,clk_50,adc_stby,adc_range,
adc_word,adc_par, adc_hw,adc_wr;
wire rst;
reg reset;
reg convst,cs,rd;
reg[3:0] state;
reg [15:0] busy_buffer;
reg [15:0] cnt;
reg R_clk50 = 0;
assign clk_50 = R_clk50 ;
reg [15:0] counter = 0;
assign adc_stby = 1;
assign adc_range = 0;
assign adc_word = 0;
assign adc_par = 0;
assign adc_hw = 0;
assign adc_wr = 0;

parameter state0=0,state1=1,state2=2,state3=3,
state4=4,state5=5,state6=6,state7=7,
state8=8, state9=9,state10=10,state11=11,
state12=12,state13=13,state14=14,state15=15;

always@ ( posedge clk_5k )
begin
if(counter <= 999) // 100进制计数器
begin
counter <= counter + 1;
end
else
begin
counter <= 0;
end
end

always@ ( posedge clk_5k )
begin
if ( counter <= 499 )
begin
R_clk50 <= 1;
end
else
begin
R_clk50 <= 0;
end
end

always @(posedge clk_5k or negedge rst)
begin
if(!rst)
begin
state <= state0;
end
else
begin
case(state)
state0:
begin
reset <= 0;
cs <= 1;
rd <= 1;
convst <= 0;
cnt <= cnt + 1;
if(cnt==2)
begin
cnt <= 0;
state <= state1;
end
else
begin
state <= state0;
end
end
state1:
begin
cs <= 1;
rd <= 1;
convst <= 1;
state <= state2;
end
state2:
begin
cnt <= cnt + 1;
if(cnt==3)
begin
cnt <= 0;
state <= state3;
end
else
begin
state <= state2;
end
end
state3:
begin
cs <= 0;
rd <= 0;
state <= state4;
end
state4:
begin
rd <= 1;
state <= state5;
end
state5:
begin
rd <= 0;
state <= state6;
end
state6:
begin
rd <= 1;
state <= state7;
end
state7:
begin
rd <= 0;
state <= state8;
end
state8:
begin
rd <= 1;
state <= state9;
end
state9:
begin
rd <= 0;
state <= state10;
end
state10:
begin
rd <= 1;
state <= state11;
end
state11:
begin
rd <= 0;
state <= state12;
end
state12:
begin
rd <= 1;
state <= state13;
end
state13:
begin
rd <= 0;
state <= state14;
end
state14:
begin;
cs <= 1;
rd <= 1;
convst <= 0;
state <= state15;
end
state15:
begin
//convst <= 1;
state <= state0;
end
default:
begin
state <= state0;
end
endcase
end
end
endmodule