xilinx_ug474_7Series_CLB阅读记录

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于 2019-02-10 15:26:42 首次发布

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本文详细介绍了FPGA设计的最佳实践，包括使用HDL进行资源推断，考虑流水线以提高性能，以及如何有效利用专用资源如DSP48E切片进行数学运算。探讨了控制输入共享、移位寄存器和小内存实现方法，并概述了推荐的设计流程步骤。

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文章目录

- Recommended Design Flow
- Carry Logic Applications/DSP48E

Recommended Design Flow

CLB resources are inferred for generic design logic and do not require instantiation. Good HDL design is sufficient. A few items to note:

CLB flip-flops have either a set or a reset. The designer must not use both set andreset.
Flip-flops are abundant. Pipelining should be considered to improve performance.
Control inputs are shared across a slice or CLB. The number of unique control inputs required for a design should be minimized. Control inputs include clock, clock enable,set/reset, and write enable.
A 6-input LUT can be used as a 32-bit shift register for efficient implementation.
A 6-input LUT can be used as a 64 x 1 memory for small storage requirements.
Dedicated carry logic implements arithmetic functions effectively.

These steps indicate the recommended design flow:

Implement the design using preferred methodologies (HDL, IP, etc.).
Evaluate utilization reports to determine resources used.Check to make sure arithmetic logic, distributed RAM, and SRL are used, when helpful.
Consider flip-flop usage.
a. Pipeline for performance.
b. Use dedicated flip-flops at the outputs of dedicated resources (block RAM, DSP)
c. Allow shift registers to use SRL (avoid set/resets)
Minimize the use of set/resets

Carry Logic Applications/DSP48E

Designs that include simple counters, comparators or adder/subtractors automatically infer the carry logic. A small arithmetic function can be faster and lower power using the CLB carry logic rather than using an entire DSP48E1 slice.

The DSP48E1 slices support many independent functions including multiply, multiply accumulate, multiply add, three-input add, barrel shift, wide-bus multiplexing, magnitude comparator, bitwise logic functions, pattern detection, and wide counter. The architecture also supports cascading multiple DSP48E1 slices to form wide math functions, DSP filters, and complex arithmetic.

The carry logic runs vertically up every other column of slices (SLICEL and SLICEM). The Xilinx tools automatically place logic in a column when the carry logic is used.