译码器的门级建模

1.新建一个文件夹，命名为DEC2x4

2.新建一个新的工程，选择Verilog HDL File

3.输入代码
module DEC2x4 (Z,A,B,Enable );
output [3:0] Z;
input A,B,Enable;
wire Abar,Bbar;

not
not0 (Abar,A),
not1 (Bbar,B);
nand
nand0(Z[3],Enable,A,B),
nand1(Z[0],Enable,Abar,Bbar),
nand2(Z[1],Enable,Abar,B),
nand3(Z[2],Enable,A,Bbar);

endmodule

module tb_22;
reg a,b,e;
wire [3:0] z;

initial
begin
a=0;b=0;e=0;
#10 a=0;b=0;e=1;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
#10 a=1’bx;b=1’bx;
#10 $stop;
end

DEC2x4 my_dec2x4 (z,a,b,e);
endmodule

4.开始进行运行