HDLBits_Module cseladd

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本文介绍如何使用提供的add16模块构建一个高效的32位加法器，通过 Carry-Select 结构改进传统 Ripple-Carry 加法器，减少延迟，提高运算速度。关键步骤包括使用二选一数据选择器根据低16位进位决定高16位的处理方式。

One drawback of the ripple carry adder (See previous exercise) is that
the delay for an adder to compute the carry out (from the carry-in, in
the worst case) is fairly slow, and the second-stage adder cannot
begin computing its carry-out until the first-stage adder has
finished. This makes the adder slow. One improvement is a carry-select
adder, shown below. The first-stage adder is the same as before, but
we duplicate the second-stage adder, one assuming carry-in=0 and one
assuming carry-in=1, then using a fast 2-to-1 multiplexer to select
which result happened to be correct.

In this exercise, you are provided with the same module add16 as the
previous exercise, which adds two 16-bit numbers with carry-in and
produces a carry-out and 16-bit sum. You must instantiate three of
these to build the carry-select adder, using your own 16-bit 2-to-1
multiplexer.

Connect the modules together as shown in the diagram below. The
provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0]
sum, output cout );

在这里插入图片描述
题目基本意思是让你实现一个32位加法器，题目已经提供好了add16，只不过在进行高16位的计算时要根据低16位的进位，通过一个二选一数据选择器来确定高16位
错误点：
直接将低16位的进位用作高16位的进位
结果是正确的但是无法通过测试点，因为这个二选一数据选择器选择顺序恰好和进位一致。提交会显示
在这里插入图片描述

正确代码

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout;
    wire [15:0] buffer1,buffer2;
    add16 u1(a[15:0],b[15:0],1'b0,sum[15:0],cout);
    add16 u2(a[31:16],b[31:16],1'b0,buffer1);
    add16 u3(a[31:16],b[31:16],1'b1,buffer2);
    assign sum[31:16] = cout? buffer2:buffer1;
    
        

endmodule
module add1(input a,input b,input cin,output sum,output cout);
    assign sum = a^b^cin;
    assign cout = a&b | a&cin | b&cin;
endmodule