jieyannn的博客

三态门LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY tri_gate IS PORT(DIN,EN:IN std_logic; DOUT: OUT std_logic);END tri_gate;ARCHITECTURE rtl OF tri_gate ISBEGIN PROCESS(DIN,EN) BEGIN ...

LIBRARY IEEEUSE IEEE.STD_LOGIC_1164.ALL;ENTITY adder IS PORT(clk :IN STD_LOGIC; out :INOUT STD_LOGIC_VECTOR(3 DOWNTO 0));END adder;LIBRARY dataio; --库声明USE dataio.STD_LOGIC_OPS.ALL;ARCHITE...

ENTITY nand_N IS GENERIC(N:INTERGER); PORT(Din:IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Dout:OUT STD_LOGIC);END ENTITY nand_N;若要求为3输入与非门，则可用类属映射语句来指定nand_N GENERIC MAP(N=>3)...

--半加器是实现两个一位二进制数的加法运算电路--对两个输入数据位相加，输出一个结果位和进位，没有进位输入LIBRARY IEEE;USE IEEE_STD_LOGIC_1164.ALL;--half_adder端口配置:--输入口：data1,data2--输出口：sum结果,carry进位ENTITY half_adder ISPORT(data1,data2:IN STD_...