vcs Options

-lca
-lca 表示使用vcs的用户限制的功能
+lca，使用一些vcs提供的最新的feature

Compile-Time Options

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-ad=<partition_filename>
Specifies the partition files used in mixed signal simulation.

-ams
Enables the use of Verilog-AMS code in VCS 2-step mode.

-ams_discipline <discipline_name>
Specifies the default discrete discipline in VerilogAMS in VCS 2-step mode.

-ams_iereport
Provides the auto-inserted connect modules (AICMs) information in VCS 2-step mode.

-as
Specifies an alternative assembler. Only applicable in incremental
compile mode, which is the default. Not supported on IBM RS/6000 AIX.

-ASFLAGS
Passes options to assembler. Not supported on IBM RS/6000 AIX.

-assert <keyword_argument>
The keyword arguments and what they do are as follows:

disable_cover
Disables coverage for SVA cover statements.

dumpoff
Disables the dumping of SVA information in the VPD file.

dve
Enables SystemVerilog assertions tracing in the VPD file
that you load into DVE. This tracing enables you to see
assertion attempts.

enable_diag
Enables further control of SystemVerilog assertions result
reporting with runtime options.

filter_past
Ignores SystemVerilog assertion subsequences containing past
operators that have not yet eclipsed the history threshold.

vpiSeqBeginTime
Enables you to see the simulation time that a SystemVerilog
assertion sequence starts when using Verdi.

vpiSeqFail
Enables you to see the simulation time that a SystemVerilog
assertion sequence does not match when using Verdi.

-C
Stops after generating the intermediate C or assembly code.

-cc
Specifies an alternative C compiler.

-CC
Works the same as -CFLAGS.

-CFLAGS
Pass options to C compiler. Multiple -CFLAGS are allowed. Allows
passing of C compiler optimization levels.

-cm line|cond|fsm|tgl|branch|assert
Specifies compiling for the specified type or types of coverage.
The arguments specifies the types of coverage:
line Compile for line or statement coverage.
cond Compile for condition coverage.
fsm Compile for FSM coverage.
tgl Compile for toggle coverage.
branch Compile for branch coverage
assert Compile for SystemVerilog assertion coverage.

If you want VCS to compile for more than one type of coverage,
use the plus (+) character as a delimiter between arguments,
for example:
-cm line+cond+fsm+tgl

-cm_assert_hier
Limits SystemVerilog assertions coverage to the module instances
listed in the specified file.

-cm_cond
Modifies condition coverage as specified by the argument or
arguments:
basic Only logical conditions and no multiple conditions.
std The default: only logical, multiple, sensitized conditions.
full Logical and non-logical, multiple conditions, no sensitized
conditions.
allops Logical and non-logical conditions.
event Signals in event controls in the sensitivity list position
are conditions.
anywidth Enables conditions that need more than 32 bits.
for Enables conditions if for loops.
tf Enables conditions in user-defined tasks and functions.
sop Condition SOP coverage instead of sensitized conditions.
also tells VCS that when it reads conditional expressions
that contain the ^ bitwise XOR and ~^ bitwise XNOR
operators, it reduces the expression to negation and
logical AND or OR.
You can specify more than one argument. If you do use the + plus
delimiter between arguments, for example:
-cm_cond basic+allops

-cm_constfile
Specifies a file listing signals and 0 or 1 values. VCS compiles for
line and condition coverage as if these signals were permanently at
the specified values and you included the -cm_noconst option.

-cm_count
Enables accounting of the following:
In toggle coverage, not just whether a signal toggled from 0 to 1 and
1 to 0, but also the number of times it so toggled.
In FSM coverage, not just whether an FSM reached a state, had such a
transition, but also the number of times it did.
In condition coverage, not just whether a condition was met or not,
but also the number of times the condition was met.
In Line Coverage, not just whether a line was executed, but also the
number of times.

-cm_glitch
Specifies a glitch period during which VCS does not monitor for
coverage caused by value changes. The period is an interval of
simulation time specified with a non-negative integer.

-cm_dir <directory_path_name>
Specifies an alternative name and location for the coverage
database directory.
-cm_fsmcfg
Specifies an FSM coverage configuration file.

-cm_fsmopt <keyword_argument>
The keyword arguments are as follows:

allowTmp
Allows FSM extraction when there is indirect assignment to the
variable that holds the current state.

configonly
Disables extraction of FSMs automatically and through FSM pragmas.
FSMs will be prepared only on the basis of the entries in FSM
config file specified through the -cm_fsmcfg option.

report2StateFsms
By default VCS does not extract two state FSMs. This keyword
tells VCS to extract them.

reportvalues
Specifies reporting the value transitions of the reg that holds
the current state of a One Hot or Hot Bit FSM where there are
parameters for the bit numbers of the signals that hold the
current and next state.

reportWait
Enables VCS to monitor transitions when the signal holding the
current state is assigned the same state value.

reportXassign
Enables the extraction of FSMs in which a state contains the X
(unknown) value.

sequence
Enables compilation and monitoring of sequence coverage. Along
with states and transitions, sequences covered during simulation
will also be recorded.

stopConcatCase
Ignores FSMs in which concatenation is used in the
case expression.

stopSelectInPackedMDA
Ignores FSMs in which select is applied on multi dimensional packed
node.

upto64
Restricts extraction of FSMs in which the width of the FSM variable
does not exceed 64 bits.

-cm_fsmresetfilter
Filters out the transitions in FSM coverage which occurs in
assignments controlled by if statements where the conditional
expression (following the if keyword) is a signal specified
in the file. This filtering out can be on the specified signal
in any module or the module specified in the file. The FSM
and whether the signal is true or false can also be specified.

-cm_hier
When compiling for line, condition, FSM or toggle coverage, specifies
a configuration file that specifies module definitions, source files,
or module instances and their subhierarchies, that you want VCS to
exclude from coverage or be the only parts of the design compiled for
coverage.

-cm_ignorepragmas
Tells VCS to ignore pragmas for coverage metrics.

-cm_report
The arguments are as follows:

unencrypted_hierarchies
compile time options to enable monitoring coverage for encrypted
designs

noinitial
compile-time option to disable the the monitoring of the contents
of initial blocks for line, condition, branch, and path metrics

-cm_libs yv|celldefine
Specifies compiling for coverage source files in Verilog libraries
when you include the yv argument. Specifies compiling for coverage
module definitions that are under the `celldefine compiler directive
when you include the celldefine argument. You can specify both
arguments using the plus (+) delimiter.

-cm_line
Modifies line coverage as specified by the argument or
arguments:
contassign Enables line coverage for continuous assignments
svtb Enables line coverage for programs and class function/tasks
You can specify more than one argument. If you do use the + plus
delimiter between arguments, for example:
-cm_line contassign+svtb

-cm_noconst
Tells VCS not to monitor for conditions that can never be met or
lines that can never execute because a signal is permanently at
a 1 or 0 value.

-cm_seqnoconst
Enables a more sophisticated constant analysis compared to
-cm_noconst. This includes analysis of non-blocking
assignments and continuous assignments with delays, as well as
handling multiple assignments to the same bits of a signal. As
with -cm_noconst, coverable objects that VCS detects can
never be hit are marked “unreachable” in coverage reports and
removed from the computation of the coverage score.

-cm_tglfile
Specifies displaying at runtime a total toggle count for one or
more subhierarchies specified by the top-level module instance
entered in the file.

-cm_tgl mda
Enables toggle coverage for Verilog 2001 and SystemVerilog unpacked
multidimensional arrays.

-cpp
Specifies a C++ compiler.

-debug_access
Enables dumping to FSDB/VPD, and limited read/callback capability.
Use’-debug_access+class’ for testbench debug, and ‘-debug_access+all’
for all debug capabilities. Refer the VCS user guide for more granular
options for debug control under the switch ‘-debug_access’ and refer to
‘-debug_region’ for region control."

-debug_pp
Enables dumping to FSDB/VPD, and use of UCLI, VERDI and DVE.

-debug
Same as -debug_pp, but also including ‘force’ capability

-debug_all
Enables all debug and dumping capability.

-dve_opt <dve_option>
You can use the argument called -dve_opt to pass DVE arguments from
simv to DVE. Each DVE argument must be preceded by -dve_opt argument.
In cases where the argument requires an additional option, the = sign
needs to be used.(E.g. -dve_opt -session=file.tcl)

-e <new_name_for_main>
Specifies the name of your main() routine in your PLI application.

-f
Specifies a file that contains a list of pathnames to source files
and compile-time options.

-F
Same as the -f option but allows you to specify a path to the file
and the source files listed in the file do not have to be absolute
pathnames.

-file filename
This option is for problems you might encounter with entries in
files specified with the -f or -F options. This file can contain
more compile-time options and different kinds of files. It can
contain options for controlling compilation and PLI options and
object files. You can also use escape characters and meta-
characters in this file, like $, `, and ! and they will expand,
for example:

-CFLAGS '-I$VC{S}_{H}OME/in$