对于MIPS的MMU和Memory Management, the first and yet important one we need always keep in mind is: No real-mode
没有实模式。这一点是MIPS CPU 的一个很重要的特点(或缺点)。
我们会问了:BNN,Give me a break. Without CPU running in the real-mode, how could you boot up a kernel? Well, here is the thing:
Bydefault, MIPS architecture , when power on, has enabled/mapped two memory areas. In other words, those two memory areas are the places where your boot codes HAVE TO resident and run on top of. If you read the makefiles of MIPS linux source tree, you would easily find the infor. For example, 0x8000xxxx or some things like that.
*kseg0 512M(From 0x8000 0000 to 0xA000 0000) are DIRECTLY mapped to phyiscal memory ranging from 0x0000 0000 to 0x2000 0000, with cache-able(either write back or write through, which is decided by SR(Status Register of MIPS CPU)
*kseg1 512M(From 0xA000 0000 to 0xC000 0000) are (also) DIRECTLy mapped to physical memory ranging from 0x0000 0000 t0 0x2000 0000, with non-cachable.
以上两点对于理解MIPS OS的启动是至关重要的。细心的读者会发现:kseg1有点象
其他CPU的real-mode方式。
*(虚拟)地址from 0x0000 0000 to 0x8000 0000 是不可以存取的,在加电时(POWER ON)!必须等到MMU TLB初始化之后才可以。
*同理对地址from 0xC000 0000 to 0xFFFF 0000
*MIPS的CPU运行有3个态--User Mode; Supervisor Mode and Kernel Mode. For simplicity, let's just talk about User Mode and Kernel Mode. Please always keep this in mind:
CPU can ONLY access kuseg memory area when running in User Mode CPU MUST be in kernel mode or supervisor mode when visiting kseg0, kseg1 and kseg2 memory area.
* MMU TLB
MIPS CPU通过TLB 来translates all virtual addresses generated by the CPU.对 于这一点,这里不多废话。
下面谈谈ASID(Address Space Identifier). Basically, ASID, plus the VA(Virtual Address) are composed of the primary key of an TLB entry. 换句话说,虚拟 地址本身是不能唯一 确定一个TLB entry的。一般而言,ASID的值就是相应的process ID.
Note that ASID can minimized TLB re-loads, since several TLB entries can have the same virtual page number, but different ASID's. 对于一个多任务操 作系统来讲,每个任务都有 自己的4G虚拟空间,但是有自己的ASID。
由于MIPS的CACHE属性是Virtually Indexed, Physically tagged.所以,任何地址的访问,CPU都会issue the request to MMU for TLB translation to get the correct physical address, which then will be used for level cache matching.