NET2272.C 代码分析——SetProcessorSpecificDefaultConfiguration-优快云博客

section("L1_code") int SetProcessorSpecificDefaultConfiguration(ADI_NET2272_DEVICE *pDev) { /* enable async bank 3 */ *pEBIU_AMGCTL |= 0xF; ssync(); /* default settings, one should be able to change through device controls before issuing USB_CMD_START */ #if defined(__ADSPBF533__) pDev->DmaStreamID = ADI_DMA_MDMA_0; pDev->PeripheralID = ADI_INT_PFA; pDev->PF_Reset = PF11; pDev->PF_Int = PF10; pDev->PF_Clear = 0; pDev->PF_Set = 0; pDev->PeripheralIVG = ik_ivg13; /* use default by querying the SSL */ #elif defined(__ADSPBF537__) pDev->DmaStreamID = ADI_DMA_MDMA_0; pDev->PeripheralID = ADI_INT_PORTFG_A; pDev->PF_Reset = PF6; pDev->PF_Int = PF7; pDev->PF_Clear = 0; pDev->PF_Set = 0; pDev->PeripheralIVG = ik_ivg13; /* use default by querying the SSL */ #elif defined(__ADSPBF561__) pDev->DmaStreamID = ADI_DMA_MDMA2_0; pDev->PeripheralID = ADI_INT_PF0_15_A; pDev->PF_Reset = PF11; pDev->PF_Int = PF10; pDev->PF_Clear = PF12; /* PF12 used by USB EZ-EXTENDER to indicate we are connected to BF561 EZ-KIT */ pDev->PF_Set = 0; pDev->PeripheralIVG = ik_ivg13; /* use default by querying the SSL */ #else #error *** Processor not supported *** #endif return 0; }

本函数的作用是对NET2272与ADSP的接口进行配置。

首先要使能内存异步块3

*pEBIU_AMGCTL |= 0xF;

ssync();

Asynchronous Memory Global
Control Register (EBIU_AMGCTL)

The Asynchronous Memory Global Control register configures global aspects of the controller. It contains bank enables and other information as described in this section. This register should not be programmed while the AMC is in use. The EBIU_AMGCTL register should be the last control register written to when configuring the processor to access external memory-mapped asynchronous devices. Writes to this register should be followed by an SSYNC instruction to ensure that the asynchronous bank is enabled before an access is attempted.

Figure 16-3. Asynchronous Memory Global Control (EBIU_AMGCTL)

Within the EBIU_AMGCTL register, the AMCKEN bit is used for external devices that are connected to CLKOUT. When it is needed, the CLKOUT/SCLK1 pin can be enabled by setting the AMCKEN bit in the EBIU_AMGCTL register. In systems that do not use CLKOUT/SCLK1, set the AMCKEN bit to 0.

Writing a “1” to the AMBEN2–0 bits will enable specific asynchronous memory banks, while a writing a “0” will disable specific banks. If a bus operation accesses a disabled asynchronous memory bank, the EBIU responds by acknowledging the transfer and asserting the error signal on the requesting bus. The error signal propagates back to the requesting bus master. This generates a hardware exception to the core, if it is the requester. For DMA mastered requests, the error is captured in the respective status register. If a bank is not fully populated with memory, then the memory likely aliases into multiple address regions within the bank. This aliasing condition is not detected by the EBIU, and no error response is asserted.

The 16-bit packing enable bits (B0PEN, B1PEN, B2PEN and B3PEN) are available to control the access size for each asynchronous memory bank separately. When one of these bits is set to one, any request to the corresponding AMC (Asynchronous Memory Controller) bank will result in a 16-bit access to external devices. Regardless of whether the request comes from a 8-bit, 16-bit, 32-bit data fetch or whether the fetch originates from the DMA controller, the EBIU will perform a 16-bit access. In the case of 32-bit requests to the AMC, a dual 16-bit access will be made to fetch 32-bits.

For more details on the use of ABE3–0, please refer to "Byte Enables" on another page.

When a 16-bit packing enable bit is set to zero (that is, “cleared”), the AMC treats any request to the dedicated bank as a 32-bit access to external device. Regardless of the kind of access (8,16 or 32-bit fetch), the external bus will perform a 32-bit access.

The CDPRIO bit configures the AMC to control the priority requests that occur simultaneously to the EBIU from either the processor core or the DMA controller. When this bit is set to zero, requests from either core have priority over a request from the DMA controller to the AMC, unless the DMA is “urgent”. When the CDPRIO bit is set, all requests from the DMA controllers, including the memory DMAs, have priority over core accesses. For the purposes of this discussion, core accesses include both data fetches and instruction fetches.