function! AlignVerilogSignals() range
let s:max_type = 0
let s:max_reg = 0
let s:max_bits = 0
let s:max_name = 0
let s:port_list = []
let signal_lines = getline(a:firstline, a:lastline)
" 解析阶段保持不变
for raw_line in signal_lines
let line = substitute(raw_line, '\s*$', '', '')
if line =~ '^\s*//'
call add(s:port_list, {'type': 'comment', 'content': line})
continue
elseif line =~ '^\s*$'
call add(s:port_list, {'type': 'blank'})
continue
endif
let clean_line = substitute(line, '\s*//.*$', '', '')
let clean_line = substitute(clean_line, '^\s*,', '', '')
let parts = matchlist(clean_line,
\ '^\s*\(logic\|bit\|reg\|wire\)\?\s*\(\[.*\]\)\?\s*\(\w\+\)')
if !empty(parts)
let name = substitute(parts[3], '\s*;.*', '', '')
let regwire = !empty(parts[1]) ? parts[1] : ''
let bits = !empty(parts[2]) ? substitute(parts[2], '\t', ' ', 'g') : ''
let comment = matchstr(line, '//.*$')
let s:max_reg = max([s:max_reg, len(regwire)+1])
let s:max_bits = max([s:max_bits, len(bits)])
let s:max_name = max([s:max_name, len(name)])
call add(s:port_list, {
\ 'type': 'port',
\ 'regwire': regwire,
\ 'bits': bits,
\ 'name': name,
\ 'comment': comment})
endif
endfor
" 生成阶段添加位宽前补足逻辑
let formatted = []
let s:last_blank = 0
for item in s:port_list
if item.type == 'comment'
call add(formatted, item.content)
let s:last_blank = 0
elseif item.type == 'blank'
if !s:last_blank
call add(formatted, '')
let s:last_blank = 1
endif
else
let port = item
" 新增位宽前补足12字符逻辑
let reg_str = printf('%-'.s:max_reg.'s', port.regwire)
let pad_after_reg = repeat(' ', max([12 - s:max_reg, 0])) " 新增补足逻辑
let bit_str = printf('%-'.s:max_bits.'s', port.bits)
let name_str = printf('%-'.s:max_name.'s', port.name)
" 组合带补足空格的新前缀
let prefix_part = reg_str . pad_after_reg . bit_str . ' ' " 修改组合方式
let prefix_length = strlen(prefix_part)
let padding = repeat(' ', max([30 - prefix_length, 0]))
let line = prefix_part . padding . name_str . ' ;'
if !empty(port.comment)
let line .= repeat(' ', 2) . port.comment
endif
let line = substitute(line, '\t', ' ', 'g')
let line = substitute(line, '\s\+$', '', '')
call add(formatted, line)
let s:last_blank = 0
endif
endfor
execute a:firstline.','.a:lastline.'d'
call append(a:firstline-1, formatted)
endfunction
" 保持快捷键定义不变
command! -range AlignSignals <line1>,<line2>call AlignVerilogSignals()
vnoremap <silent> <leader>as :AlignSignals<CR>
nnoremap <silent> <leader>as :AlignSignals<CR>
优化以上脚本，只有符合信号声明语法的才进行对齐，不符合的就维持原样。
做最少的修改，修改完成后输出完整脚本
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