Control Traffic Trapping/Mirroring to the CPU
Protocols implemented in software require specific control traffic to be trapped or mirrored to the
CPU.
The device provides trapping/mirroring mechanisms for many well
-known control traffic protocols.
Other control traffic that does not have specific support can be trapped/mirrored to the CPU by the
Policy engine.
A global configuration disables the following controls for packets that were dropped by the Spanning
Tree:
IGMP
MLD
and Other IPv6 ICMP
UDP Broadcast Mirror/Trap (UDP Relay)
IP Interface Control Traffic
Configuration
To disable L3 Controls for packets that were dropped by the Spanning Tree, set the
<DisableIPControltoCPUforSTP> field in the Bridge Global Configuration1 Register (Table 320
p. 2218).
10.8.1 Layer 2 Interface Unicast Management Traffic
Layer 2 interface Unicast management traffic arrives with a MAC DA set to the management MAC
address on a given eVLAN interface.
Typical examples of Unicast management traffic are:
IP management protocols like SNMP, HTTP,
and ICMP
ARP Reply packets
To direct Unicast Management Traffic to the CPU, the FDB is configured with an entry as follows:
<MAC Address> = management Unicast MAC Address
<FID> = The Forwarding ID of the management VLAN interface
<DA Comm
and> = FORWARD
<ePort number> = CPU port 63 (refer to Section 23.1, CPU Port)
<Application Specific CPU Code Enable> =1
<static> = 1
Packets with MAC DA matching the management Unicast MAC Address are sent to the CPU with
the CPU code BRIDGED_PACKET_FORWARD. However, if the FDB entry <Application Specific
CPU Code Enable> is set, the CPU code may be overridden by a finer
-grain CPU code. For
example, if the packet is an ARP reply, its CPU code assignment can be overridden with the specific
CPU code ARP_REPLY_TO_ME. This is performed in the Pre
-Egress stage of the Ingress pipeline
(Section 23.2.4, Application
-Specific CPU
Codes).
Refer to Section 10.4.7.2, FDB Table Read/Write Access for details on how the FDB is updated.
Note
When the FDB entry <port number> is set to the CPU port 63, the FDB entry <device
number> is not
relevant, as the packet is forwarded to the target device according to
the CPU code table configuration, as described in Section 23.2.5, CPU Code Table. IPv4/6
and FCoE Interface for Routed Traffic
Bridged traffic with a MAC DA of the router interface is subject to
processing by the Router engine,
per the Router Engine Trigger (refer to Section 11.2, Router Engine Trigger).
This traffic may be inbound management traffic with the Unicast destination IP address of the router,
or other IP traffic that requires routing to its next
-hop interface. It may also be FCoE traffic that is
subjected to FCoE Forwarding (FCF) by the Router engine.
The FDB is configured with a static Unicast Router MAC address for each eVLAN interface enabled
for routing.
The FDB Router MAC entry is configured as follows:
<MAC Address> = Unicast Router MAC address
<FID> = The Forwarding ID of the management VLAN interface
<static> = 1
<DA Route>=1, indicating that the entry Unicast MAC Address is the Router MAC
<DA Comm
and>=FORWARD
<Device Number> = local device
<ePort Number>= CPU port (63)
<Application Specific CPU Code Enable> =1
The Router MAC FDB entry serves two purposes:
The <DA Route> bit serves as input to the Router engine trigger check to determine whether
the packet is eligible for routing. If the packet is subsequently routed by the Router engine, the
bridge forwarding decision (CPU port 63) is overridden by the router next
-hop information.
If the packet does not trigger the Router engine for any other reason (for example, packet is not
non
-IP), the packet is sent to CPU port 63, with the CPU code
BRIDGED_PACKET_FORWARD. However, if the FDB entry <Application Specific CPU Code
Enable> is set, the CPU code may be overridden by a finer
-grain CPU code, for example, if the
packet is an ARP reply, its CPU code assignment can be overridden with the specific CPU code
ARP_REPLY_TO_ME. This is performed in the Pre
-Egress stage of the Ingress pipeline
(Section 23.2.4, Application
-Specific CPU
Codes).
10.8.3 IEEE Reserved Multicast
IEEE 802.1D/Q defines the following reserved Multicast MAC ranges:
Bridge St
andard Protocols: 01
-80
-C2
-00
-00
-00
- 01
-80
-C2
-00
-00
-0F
Bridge GARP Applications: 01
-80
-C2
-00
-00
-20
- 01
-80
-C2
-00
-00
-2F
Common addresses that fall into these ranges are listed in Table 28.
Table 28: IEEE Reserved Multicast Addresses
Protocol Identified by
IEEE 802.1Q BPDU DA=01
-80
-C2
-00
-00
-00
IEEE 802.3 Slow Protocols (for example, LACP) DA=01
-80
-C2
-00
-00
-02
IEEE 802.1X PAE address DA=01
-80
-C2
-00
-00
-03
IEEE 802.1Q Provider BPDU DA=01
-80
-C2
-00
-00
-08
IEEE 802.1Q Provider Bridge GVRP DA=01
-80
-C2
-00
-00
-0D
IEEE 802.1AB LLDP DA=01
-80
-C2
-00
-00
-0E As a generic mechanism to trap or mirror the above reserved IEEE ranges
and possible future IEEE
protocols, the device supports 8 IEEE Reserved Multicast Comm
and tables.
A packet is considered an IEEE Reserved Multicast packet if its MAC destination address is in the
range 01
-80
-C2
-00
-00
-XX.
Each ePort is configured to utilize one of these 8
tables to
process IEEE Reserved Multicast
packets.
If a packet is identified as an IEEE Reserved Multicast packet (its MAC destination address is in the
range 01
-80
-C2
-00
-00
-XX) then:
The respective IEEE Reserved Multicast comm
and table is indexed by the last byte of the
Multicast address. The comm
and for each entry can be set to:
• SOFT DROP
• FORWARD
• MIRROR
• TRAP
A configuration (indexed by the last byte of the Multicast address) defines if the packet is
treated as Registered MC (refer to Section 10.14.1.3, Bridge Phase 1 Modification of the
Unregistered/Unknown Status).
To enable differentiation between different types of IEEE Reserved Multicast packets that are either
trapped or mirrored to the CPU, there is a configurable 2
-bit <CPU code index>, described in
Table 29, assigned to the packet based on table entry index, meaning that the value of the last byte
of the MAC destination address.
The same <CPU Code Index> assignment is applied independently of the binding to one of the 8
IEEE Reserved Multicast
tables.
Configuration
To configure the IEEE Reserved Multicast comm
and, set the respective IEEE Reserved
Multicast table entry via one of the 8 available
tables:
• IEEE Reserved Multicast Configuration0 <n> Register (n=0–15) (Table 335 p. 2232)
• IEEE Reserved Multicast Configuration1 <n> Register (n=0–15) (Table 336 p. 2234)
• IEEE Reserved Multicast Configuration2 <n> Register (n=0–15) (Table 337 p. 2236)
IEEE 802.1D GMRP DA=01
-80
-C2
-00
-00
-20
IEEE 802.1Q GVRP DA=01
-80
-C2
-00
-00
-21
Table 29: IEEE Reserved Multicast CPU Code Assignment
<CPU Code Index> CPU Code Assignment
0 IEEE_RES_MC_ ADDR_TRAP/MIRROR_0
1 IEEE_RES_MC_ ADDR_TRAP/MIRROR_1
2 IEEE_RES_MC_ ADDR_TRAP/MIRROR_2
3 IEEE_RES_MC_ ADDR_TRAP/MIRROR_3 IEEE Reserved Multicast Configuration3 <n> Register (n=0–15) (Table 338 p. 2238)
• IEEE Reserved Multicast Configuration4 <n> Register (n=0–15) (Table 339 p. 2241)
• IEEE Reserved Multicast Configuration5 <n> Register (n=0–15) (Table 340 p. 2243)
• IEEE Reserved Multicast Configuration6 <n> Register (n=0–15) (Table 341 p. 2245)
• IEEE Reserved Multicast Configuration7 <n> Register (n=0–15) (Table 342 p. 2247)
To configure for IEEE Reserved Multicast address, if packets to that address are considered
registered, set the respective bit in the IEEE Reserved Multicast Registered <n> (n=0–7)
(Table 344 p. 2250)
Select one of the 8
tables to be utilized by each ePort by configuring the <IEEE Reserved MC
table select> field in the Ingress Bridge ePort Table (Table 392 p. 2333).
To set the CPU code index for each IEEE Reserved Multicast address, configure the
relevant
fields in IEEE Reserved Multicast CPU Index <n> Register (n=0–15) (Table 343 p. 2249).
10.8.3.1 FDB Learning of Trapped or Dropped IEEE Reserved Multicast
Packets
When two bridges are connected to each other by more than a single port, IEEE
-reserved MC
packets are received by the bridge on all ports connecting between the two bridges. The IEEE
802.1Q st
andard requires the bridges to send the IEEE
-reserved MC packets with unique MAC SA
per port.
There are bridges that use the same MAC SA for all the ports. This triggers continuous moved
address indications
and related
processing in the receiving bridge. To protect those bridges from
constantly
processing the moved address for IEEE
-reserved MC packets, the user can configure the
device not to perform MAC SA learning for reserved IEEE MC packets that are dropped or trapped
to the CPU.
Configuration
To enable/disable this feature, use the<EnLearnOnTrapIEEEReservedMC> field in the Ingress
Bridge ePort Table (Table 392 p. 2333).翻译一下
SD流程详解
本文详细介绍了SD（销售与分销）流程中的关键步骤，包括询价、报价、销售订单、交货及发票等环节，并阐述了各步骤所涉及的主要SAP交易代码及对应的后台表。
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