Freescale mx27 DDR 初始化代码分析

在DDRSDRAM能够被存取数据之前，需要先对其初始化。该初始化流程是预先定义好的，不正确的操作将导致无法预料的结果。初始化的过程中将设置DDRSDRAM的普通模式寄存器和扩展模式寄存器，用来制定DDRSDRAM的工作方式。这些设置包括突发长度、突发类型、CAS潜伏期和工作模式以及扩展模式寄存器中的对DDRSDRAM内部DLL的使能与输出驱动能力的设置。模式寄存器可以被再编程，这时需要DDR SDRAM的各个区（bank）处于空闲状态，从而改变存储器的工作模式。如果操作正确，对模式寄存器的再编程不会改变存储器内存储的数据。初始化完成之后，DDRSDRAM便进入正常的工作状态，此时便可对存储器进行读写和刷新.

以下代码是摘自mx27 redboot ddr初始化代码, 硬件采用2片HYB18M512160AF芯片组成32bit memory width:

.macro setup_sdram_ddr
ldr r0, SOC_ESDCTL_BASE_W
mov r2, #SOC_CSD0_BASE //0xA0000000
mov r1, #0x8 // initial reset
// LPDDR Delay Line is reset.
str r1, [r0, #0x10]//0xD8001010 Enhanced SDRAM Control Register 0
// Hold for more than 200ns
ldr r1, =0x10000
1:
subs r1, r1, #0x1
bne 1b

mov r1, #0x4
str r1, [r0, #0x10] //0xD8001010

//Check The chip version TO1 or TO2
ldr r1, SOC_SI_ID_REG_W
ldr r1, [r1]
ands r1, r1, #0xF0000000
// add Latency on CAS only for TO2
// TO 1.0's ID = 0x0 ==>> CAS = 3
bne 2f
ldr r1, SDRAM_0x00795729
b 3f
// now handles TO 2.x
2:
ands r1, r1, #0xE0000000
// TO 2.0's ID = 0x1 => CAS = 4 due to the MPEG4 issue
ldreq r1, SDRAM_0x00795429
//tCAS[9:8] = 2 clocks SDR and LPDDR SDRAM CAS latency2
// subesquent TO's are OK w/ CAS = 3
ldrne r1, SDRAM_0x00795729

//设置tCAS tRAStRCD等参数
//[31:23] Reserved
//tXP[22:21 = 4 clocks
//tWTR[20] = 2 clocks
//tRP[19:18] = 3 clocks
//tMRD[17:16] = 2 clocks
//tWR[15] = SRRAM 1 clocks; LPDDR 2clocks
//tRAS[14:12] = 6 clocks
//tRRD[11:10] = 2 clocks
//tCAS[9:8] = 3 clocks SDR and LPDDR SDRAM CAS latency2
//[7] Reserved
//tRCD[6:4] = 3 clocks
//tRC[3:0] = 10 clocks
3:
str r1, [r0, #0x4] //0xD8001004
ldr r1, SDRAM_0x92200000
// [31] SDRAM Controller Enable
// [30-28] SDRAM Controller Operating Mode 001=Precharge Command
// [27] Supervisor Protect
// [26:24] Row Address Width 010 -13 Row Addresses
// [23:22] Reserved
// [21:20] Column Address Width 10 -10 Column Addresses

str r1, [r0, #0x0] //0xD8001000
ldr r1, [r2, #0xF00]
ldr r1, SDRAM_0xA2200000
// [31] SDRAM Controller Enable
// [30-28] SDRAM Controller Operating Mode 010=Auto-Refresh Command
// [27] Supervisor Protect
// [26:24] Row Address Width 010 -13 Row Addresses
// [23:22] Reserved
// [21:20] Column Address Width 10 -10 Column Addresses
str r1, [r0, #0x0]
ldr r1, [r2, #0xF00]
ldr r1, [r2, #0xF00]
ldr r1, SDRAM_0xB2200000
// [31] SDRAM Controller Enable
// [30-28] SDRAM Controller Operating Mode 011=Load Mode Register Command
// [27] Supervisor Protect
// [26:24] Row Address Width 010 -13 Row Addresses
// [23:22] Reserved
// [21:20] Column Address Width 10 -10 Column Addresses
str r1, [r0, #0x0]
ldrb r1, [r2, #0x33]
add r3, r2, #0x1000000
ldrb r1, [r3]
ldr r1, SDRAM_0x82228485
// [31] SDRAM Controller Enable
// [30-28] SDRAM Controller Operating Mode 000 -Normal Read/Write
// [27] Supervisor Protect
// [26:24] Row Address Width 010=13 Row Addresses
// [23:22] Reserved
// [21:20] Column Address Width 10=10 Column Addresses
// [17:16] SDRAM Memory Data Width 10=32-bit memory width
// [15:13] SDRAM Refresh Rate - Table 18-9. 100=8 clocks
// [11:10] Power Down Timer - Table 18-10. 01=Any time no banks are active
// [8] Full Page - This bit should be set to 1 if the Burst Length of
//the SDRAM connected to the CSD has been configured to Full-Page mode.
// [7] Burst Length. 1=8
// [5:0] Precharge Timer. - Table 18-12. 000101=10 clocks to precharge
str r1, [r0, #0x0] //0xD8001000
.endm // setup_sdram_ddr