计组设计实验代码（一）

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-- Company:
-- Engineer:
--
-- Create Date:    22:02:14 09/19/06
-- Design Name:   
-- Module Name:    memory - Behavioral
-- Project Name:  
-- Target Device: 
-- Tool versions: 
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity memory is
    Port ( cs : in std_logic;
           wr : in std_logic;
           rd : in std_logic;
           data : inout std_logic_vector(3 downto 0);
              membuf : buffer std_logic_vector(3 downto 0));
end memory;

architecture Behavioral of memory is

begin
    process(wr,cs)
    begin
        if cs='1' and wr='1' then
            membuf <= data;        
        elsif cs ='1' and rd = '1' then
          data <= membuf;
        end if;

    end process;

end Behavioral;

今天实际用到的代码（测试通过）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity memory is
    Port ( cs : in std_logic ;
      wr : in std_logic;
  rd : in std_logic;
           data : inout std_logic_vector(3 downto 0);
   membuf : buffer std_logic_vector(3 downto 0):="0000"
   );
end memory;

architecture Behavioral of memory is

begin
   process(cs,wr,rd)
    begin
 if cs ='1' and wr = '1' then
  membuf <= data;
 elsif cs ='1' and rd = '1' then
  data <= membuf;
 else
  data <= "ZZZZ";
  
 end if;
    end process ;

end Behavioral;

体会是高阻那里竟然是要在波形图里设置的！