hujy23的博客

iverilog 提示 Unknown module type 的解决办法就是：include被实例化的文件名。例如设计模块是pred_core.v，仿真模块是pred_core_test.v，仿真模块实例化了pred_core模块，但是还是会报错：PS C:\Users\vid\Documents\Working\Verilog> iverilog pred_core_test.vpred_core_test.v:16: error: Unknown module type: pred_cor

Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).题目地址：Exams/ece241 2013 q4 - HDLBits我觉得不用状态机是比较简单的只.