imx6 nand Flash 启动

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最新推荐文章于 2023-08-07 16:03:23 发布 · 6.2k 阅读

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#imx6 #nand Flash #启动

本文介绍了IMX6芯片在启动过程中如何利用NAND Flash进行操作，包括启动日志的解析和相关咨询信息。

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IMX6 启动日志，欢迎来电咨询：

U-Boot 2014.04 (May 04 2016 - 09:00:06)

CPU:   Freescale i.MX6DL rev1.2 at 792 MHz
CPU:   Temperature 28 C, calibration data: 0x59250469
Reset cause: POR
Board: MX6-SabreSD
I2C:   ready
DRAM: 1 GiB
NAND: 4096 MiB
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Normal Boot
Hit any key to stop autoboot: 0

NAND read: device 0 offset 0x4000000, size 0x800000
8388608 bytes read: OK

NAND read: device 0 offset 0x5000000, size 0x100000
1048576 bytes read: OK
Kernel image @ 0x12000000 [ 0x000000 - 0x4f0fc0 ]
## Flattened Device Tree blob at 18000000
   Booting using the fdt blob at 0x18000000
   Using Device Tree in place at 18000000, end 1800e584

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 3.10.53 (huiweit@ubuntu) (gcc version 4.9.2 20140904 (prerelease) (c                                                              rosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #33 SMP PREEMP                                                              T Thu May 12 17:51:03 HKT 2016
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Freescale i.MX6 Quad/DualLite (Device Tree), model: Freescale i.MX6 Dua                                                              lLite SABRE Smart Device Board(PFUZE100)
cma: CMA: reserved 320 MiB at 3c000000
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 8 pages/cpu @814d4000 s8960 r8192 d15616 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096
Kernel command line: console=ttymxc0,115200 ubi.mtd=3 root=ubi0:rootfs rootfstyp                                                              e=ubifs mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1024MB = 1024MB total
Memory: 698008k/698008k available, 350568k reserved, 0K highmem
Virtual kernel memory layout:
    vector : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xc0800000 - 0xff000000   (1000 MB)
    lowmem : 0x80000000 - 0xc0000000   (1024 MB)
    pkmap   : 0x7fe00000 - 0x80000000   (   2 MB)
    modules : 0x7f000000 - 0x7fe00000   ( 14 MB)
      .text : 0x80008000 - 0x80bc4c34   (12020 kB)
      .init : 0x80bc5000 - 0x80c07300   ( 265 kB)
      .data : 0x80c08000 - 0x80c533a0   ( 301 kB)
       .bss : 0x80c533a0 - 0x80cbc014   ( 420 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Preemptible hierarchical RCU implementation.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
NR_IRQS:16 nr_irqs:16 16
L310 cache controller enabled
l2x0: 16 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x32050000, Cache size: 524288 B
sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655ms
CPU identified as i.MX6DL, silicon rev 1.2
Console: colour dummy device 80x30
Calibrating delay loop... 1581.05 BogoMIPS (lpj=7905280)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x8060fc00 - 0x8060fc58
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (3162.11 BogoMIPS).
CP