[Solaris内存管理]页表格式

最新推荐文章于 2025-07-03 13:06:44 发布

原创最新推荐文章于 2025-07-03 13:06:44 发布 · 1.1k 阅读

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#solaris #table #exception #numbers #access

本文探讨了PAE（Physical Address Extension）与IA-32e（Intel 64）模式下内存管理的技术细节。在PAE模式中，通过增加页目录指针表来实现对更大地址空间的支持，允许访问超过4GB的物理内存。而在IA-32e模式中，引入了PML4（Page Map Level 4）进一步扩展了地址空间。

PDE and PTE (32bit, 4-Kbyte pages)

PDE (32 bit, 4-MByte pages)

CR4.PAE = 1.
Page Size: 4KB/2MB
Linear Address is still 32bit
Paging table entries are increased to 64bits. Entry numbers decreased from 1024 to 512.
Page-Directory-Pointer Table is added.

How to access 64GByte:
Only 4GBytes is allowed to be accessed at one time
Additional 4GB sections of physical memory can be addressed in either of two way:
Change the pointer in register CR3 to point to another page-directory-pointer table, which in turn points to another set of page directories and page tables.
Change entries in the page-directory-pointer table to point to other page directories, which in turn point to other sets of page tables.

CR4.PAE should be set to 0. PSE-36 CPUID feature flag should be set
Page size: 4MB only

First implementation: 48 bits linear address  40 bits physical address
Potentially: 64 bits linear address  52 bits physical address
PML4 (page map level 4) is added on top of the page directory pointer table
PML4 (9bits) + PDP (9bits) + PDE (9bits) + PTE (9bits) + page offset (12bits)  48 bits linear address
CR4.PAE must be set to 1 before activating IA-32e
Otherwise, general-protection exception #GP.
Page Size: 4KB/2MB