HDU-2955 Robberies (01背包 入门题)

本文介绍了一个基于概率的算法问题,模拟银行抢劫的风险评估过程。目标是在被抓概率低于一定阈值的前提下,最大化抢劫所得金额。

Robberies

Time Limit: 2000/1000 MS (Java/Others)    Memory Limit: 32768/32768 K (Java/Others)
Total Submission(s): 26230    Accepted Submission(s): 9674


Problem Description
The aspiring Roy the Robber has seen a lot of American movies, and knows that the bad guys usually gets caught in the end, often because they become too greedy. He has decided to work in the lucrative business of bank robbery only for a short while, before retiring to a comfortable job at a university.


For a few months now, Roy has been assessing the security of various banks and the amount of cash they hold. He wants to make a calculated risk, and grab as much money as possible.


His mother, Ola, has decided upon a tolerable probability of getting caught. She feels that he is safe enough if the banks he robs together give a probability less than this.
 

Input
The first line of input gives T, the number of cases. For each scenario, the first line of input gives a floating point number P, the probability Roy needs to be below, and an integer N, the number of banks he has plans for. Then follow N lines, where line j gives an integer Mj and a floating point number Pj . 
Bank j contains Mj millions, and the probability of getting caught from robbing it is Pj .
 

Output
For each test case, output a line with the maximum number of millions he can expect to get while the probability of getting caught is less than the limit set.

Notes and Constraints
0 < T <= 100
0.0 <= P <= 1.0
0 < N <= 100
0 < Mj <= 100
0.0 <= Pj <= 1.0
A bank goes bankrupt if it is robbed, and you may assume that all probabilities are independent as the police have very low funds.
 

Sample Input
3 0.04 3 1 0.02 2 0.03 3 0.05 0.06 3 2 0.03 2 0.03 3 0.05 0.10 3 1 0.03 2 0.02 3 0.05
 

Sample Output
2 4 6
 

#include <bits/stdc++.h>
using namespace std;
int m[101];
double p[101], dp[10001];
int main(){
    int T;
    scanf("%d", &T);
    while(T--){
        double P;
        int n, tot = 0;
        scanf("%lf %d", &P, &n);
        for(int i = 1; i <= n; ++i){
            scanf("%d %lf", &m[i], &p[i]);
            tot += m[i];
        }
        dp[0] = 1.0;
        for(int i = 1; i <= tot; ++i){
            dp[i] = 0;
        }
        for(int i = 1; i <= n; ++i){
            for(int j = tot; j >= m[i]; --j){
                dp[j] = max(dp[j], dp[j - m[i]] * (1.0 - p[i]));
            }
        }
        for(int i = tot; i >= 0; --i){
            if(1 - dp[i] <= P){
                printf("%d\n", i);
                break;
            }
        }
    }
}

/*
题意:小偷去100家银行,偷每家都有被抓概率被抓,概率p[i],偷不同银行的事件之间相互独立。
现在小偷希望偷到更多的钱,但是被抓的概率不能超过P,问最多能偷多少钱。

思路:这题有明显的01背包的感觉,唯一不同的是这题转移用的是乘法。。。dp[i]表示偷i元最大可以
有多少的概率不被抓,因为不被抓的概率直接算相对麻烦,不如一步到位直接求不被抓的概率,这样
最后从大到小遍历i,1 - dp[i] <= p时的i就是最多能偷多少了。
转移方程:dp[j] = max(dp[j], dp[j - m[i]] * (1.0 - p[i]))。
*/


### 在 Vivado 中配置和使用 HDU-XL-01 开发板的方法 #### 1. 确定开发环境与硬件支持 HDU-XL-01 是一款基于 Xilinx FPGA 的开发板。在 Vivado 中使用该开发板时,首先需要确保所使用的 FPGA 器件型号被 Vivado 支持[^1]。例如,如果开发板采用的是 Spartan 或 Artix 系列器件,则需要选择对应的器件型号。 #### 2. 创建 Vivado 工程 在 Vivado 中创建一个新的工程,并指定目标 FPGA 器件型号为 HDU-XL-01 所使用的具体型号。通过“Create Project”向导完成工程设置,并确保选择了正确的 FPGA 器件[^1]。 #### 3. 引入开发板约束文件 为了正确映射开发板上的资源(如 LED、按键、UART 等),需要引入开发板的约束文件(XDC 文件)。如果没有现成的 XDC 文件,可以根据开发板手册手动编写约束文件。以下是一个简单的 XDC 文件示例: ```xdc # LED 约束 set_property PACKAGE_PIN L15 [get_ports {LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] set_property PACKAGE_PIN M14 [get_ports {LED[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] # 按键约束 set_property PACKAGE_PIN J15 [get_ports BTN] set_property IOSTANDARD LVCMOS33 [get_ports BTN] ``` 将此文件添加到 Vivado 工程中,并确保其正确应用到设计中[^1]。 #### 4. 设计实现 根据具体功能需求,设计相应的 Verilog 或 VHDL 模块。例如,若需要实现一个简单的 LED 闪烁功能,可以参考以下代码: ```verilog module blinky ( input wire clk, // 时钟信号 input wire reset, // 复位信号 output reg [1:0] LED // LED 输出 ); reg [24:0] counter; always @(posedge clk or posedge reset) begin if (reset) begin counter <= 25'd0; LED <= 2'b00; end else begin counter <= counter + 1'b1; if (counter == 25'd50000000) begin // 约 1 秒 counter <= 25'd0; LED <= LED + 1'b1; end end end endmodule ``` 将上述模块添加到工程中,并确保其输入输出端口与开发板约束文件中的定义一致[^1]。 #### 5. 综合、实现与生成比特流 完成设计后,在 Vivado 中依次执行综合、实现和生成比特流的操作。确保所有步骤均无错误或警告信息。完成后,生成的比特流文件将用于编程 FPGA[^1]。 #### 6. 编程 FPGA 使用 Vivado 的“Open Hardware Manager”功能连接到实际硬件设备,并将生成的比特流文件下载到 HDU-XL-01 开发板中。确保开发板已正确连接至计算机,并安装了相应的驱动程序。 #### 7. 测试功能 下载比特流后,测试开发板上实现的功能是否符合预期。例如,观察 LED 是否按照设计要求闪烁。 --- ###
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