这一系列的目的是为了梳理清楚gem5是如何将不同的体系结构的代码进行构建的,记录学习的过程。如有错误,请不吝赐教。
1 Impl
./src/cpu/o3/impl.hh
这个文件中定义了CPUPolicy,BaseO3DynInst和FullO3CPU (其模板参数又为O3CPUImpl,看起来会比较奇怪)。
struct O3CPUImpl
{
/*.....*/
/** The CPU policy to be used, which defines all of the CPU stages. */
typedef SimpleCPUPolicy<O3CPUImpl> CPUPol;
/** The DynInst type to be used. */
typedef BaseO3DynInst<O3CPUImpl> DynInst;
/** The refcounted DynInst pointer to be used. In most cases this is
* what should be used, and not DynInst *.
*/
typedef RefCountingPtr<DynInst> DynInstPtr;
typedef RefCountingPtr<const DynInst> DynInstConstPtr;
/** The O3CPU type to be used. */
typedef FullO3CPU<O3CPUImpl> O3CPU;
/*.....*/
};
我们来看看CPUPolicy是什么
./src/cpu/o3/cpu_policy.hh
template<class Impl>
struct SimpleCPUPolicy
{
/** Typedef for the freelist of registers. */
typedef UnifiedFreeList FreeList;
/** Typedef for the rename map. */
typedef UnifiedRenameMap RenameMap;
/** Typedef for the ROB. */
typedef ::ROB<Impl> ROB;
/** Typedef for the instruction queue/scheduler. */
typedef InstructionQueue<Impl> IQ;
/** Typedef for the memory dependence unit. */
typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
/** Typedef for the LSQ. */
typedef ::LSQ<Impl> LSQ;
/** Typedef for the thread-specific LSQ units. */
typedef ::LSQUnit<Impl> LSQUnit;
/** Typedef for fetch. */
typedef DefaultFetch<Impl> Fetch;
/** Typedef for decode. */
typedef DefaultDecode<Impl> Decode;
/** Typedef for rename. */
typedef DefaultRename<Impl> Rename;
/** Typedef for Issue/Execute/Writeback. */
typedef DefaultIEW<Impl> IEW;
/** Typedef for commit. */
typedef DefaultCommit<Impl> Commit;
/**......................*/
}
这个CPU Policy并没有实例化或者声明CPU的部件,只是起了别名。
而真正的创建了CPU各个单元的代码则是:
./src/cpu/o3/cpu.hh
如果同样是O3CPU,即使是同样的ISA,想要改变比如decode,fetch的方式,应当是可以直接增加新的fetch,decode类,建一个不同的CPUPolicy,然后更改O3CPUImpl中使用的CPUPolicy,即可以实现不同的decode的类型的切换。
/**
* FullO3CPU class, has each of the stages (fetch through commit)
* within it, as well as all of the time buffers between stages. The
* tick() function for the CPU is defined here.
*/
template <class Impl>
class FullO3CPU : public BaseO3CPU
{
public:
// Typedefs from the Impl here.
typedef typename Impl::CPUPol CPUPolicy;
typedef

本文深入探讨了gem5模拟器中不同体系结构代码的构建过程,详细讲解了impl与arch的结合机制,以及ISA如何影响CPU部件的配置。通过分析gem5的源代码,揭示了从Sconscript生成the_isa.hh,到impl如何获得当前ISA信息,再到如何在fetch阶段使用特定ISA的解码器。
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