Seven Languages In Seven Weeks: Week 1 (Ruby) - Day 1

本文记录了作者通过《七周七语言》一书学习Ruby的过程,包括字符串操作与循环的基础练习,以及一个猜数字游戏的实现。
打算收集这一系列的文章,好不容易发现的,感觉作者有些功力,希望能学到东西,哇咔咔!

E文一般的同学也能看懂,近期有时间会翻译一两篇。

Seven Languages In Seven Weeks: Week 1 (Ruby) - Day 1

27 Nov 2011

Out of the seven languages in this book, Ruby is the one I was most familiar with previously. It made for an easy start, and gave me a bit of momentum before I started to tackle languages like Prolog. I’m appreciative of that, because Prolog sure was a struggle for a while.

(This article is part of a series of posts I am doing about my journey through the exercises of the book Seven Languages In Seven Weeks. This article is the first one in the series. For an overview see the project page.)

Day 1 of Week 1 was pretty basic - a bit of string manipulation and looping. Ruby makes things like this very short and pretty.

For example, being able to repeat a string like: "Nick " * 10 or loop like: (1..10).each { |num| do_stuff(num) } is great.

Here is my full code listing for the exercises from Day 1 of Ruby. The home of this piece of code is with the other exercises on github.

# Find:
# 1. A method that substitutes a part of a string
puts "\nFind:"
puts "\n1."
puts "BAM".gsub "M", "TMAN"


# Do:
# 1. Print the string "Hello World"
puts "\nDo:"
puts "\n1."
puts "Hello World"

# 2. For the string "Hello, Ruby," find the index of the word "Ruby."
puts "\n2."
# literally:
p "Hello, Ruby,".index "Ruby."
# realistically:
puts "Hello, Ruby".index "Ruby"

# 3. Print your name ten times
puts "\n3."
puts "Nick " * 10

# 4. Print the string "This is sentence number 1," where the number 1 changes
# from 1 to 10
puts "\n4."
(1..10).each { |num| puts "This is sentence number #{num}" }

# Bonus: Write a program that picks a random number. Let a player guess the
# number, telling the player whether the guess is too low or too high.
puts "\nBonus:"

random_number = rand(1000) + 1
guess = 0

while guess != random_number do
    print "Pick a number between 1 and 1000: "
    guess = gets.to_i
    puts "Too low!" if guess < random_number
    puts "Too high!" if guess > random_number
end

puts "Got it! It was #{random_number}"
And the output:
$ ruby day1.rb

Find:

1.
BATMAN

Do:

1.
Hello World

2.
nil
7

3.
Nick Nick Nick Nick Nick Nick Nick Nick Nick Nick 

4.
This is sentence number 1
This is sentence number 2
This is sentence number 3
This is sentence number 4
This is sentence number 5
This is sentence number 6
This is sentence number 7
This is sentence number 8
This is sentence number 9
This is sentence number 10

Bonus:
Pick a number between 1 and 1000: 500
Too high!
Pick a number between 1 and 1000: 250
Too high!
Pick a number between 1 and 1000: 125
Too low!
Pick a number between 1 and 1000: 192
Too high!
Pick a number between 1 and 1000: 158
Too high!
Pick a number between 1 and 1000: 141
Too high!
Pick a number between 1 and 1000: 133
Too high!
Pick a number between 1 and 1000: 129
Got it! It was 129



### INFO信息含义及问题判断 #### 1. `[VRFC 10-2263] Analyzing Verilog file ... into library xil_defaultlib` 此信息表明工具正在分析指定路径下的Verilog文件,并将其内容解析到 `xil_defaultlib` 库中。这是正常的分析流程步骤,意味着工具开始对文件进行语法和语义分析,本身不代表存在问题。例如: ```verilog // 假设这是 debounce.v 文件内容 module debounce ( input wire clk, input wire reset, input wire signal_in, output reg signal_out ); // 模块内部逻辑 endmodule ``` 工具会读取这个文件并将其分析到指定库中。 #### 2. `[VRFC 10-311] analyzing module ...` 这表示工具正在对文件中的特定模块进行详细分析。同样,这是正常的分析过程,说明工具正在处理模块的端口声明、内部逻辑等内容。例如,对于 `display_controller` 模块: ```verilog module display_controller ( input wire clk, input wire [3:0] data, output reg [6:0] seg ); // 模块内部逻辑 endmodule ``` 工具会对该模块进行分析,检查语法和逻辑是否正确。 #### 3. `[VRFC 10-8497] literal value 'd4 truncated to fit in 2 bits` 这是一个警告信息,表明在代码中尝试将一个超出变量位宽的值赋给该变量。例如: ```verilog reg [1:0] state; assign state = 2'd4; // 2 位寄存器无法容纳 4(二进制 100),会截断为 00 ``` 这种情况可能会导致数据丢失,需要检查代码中变量的位宽声明和赋值操作,确保位宽匹配。 #### 4. `[VRFC 10-4982] syntax error near 'endmodule'` 和 `[VRFC 10-8549] Verilog 2000 keyword 'endmodule' used in incorrect context` 这是错误信息,说明在 `endmodule` 关键字附近存在语法问题。可能的原因包括: - 代码块未正确闭合,如 `begin` 没有对应的 `end`,`case` 没有对应的 `endcase` 等。 - 拼写错误,如 `endmodule` 写成了 `endmodul` 等。 - 注释未正确闭合,影响了代码的语法结构。 例如: ```verilog module example ( input wire clk ); always @(posedge clk) begin // 代码逻辑 // 缺少 end endmodule // 这里会报错 ``` ### 相关问题
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