Intel FPGA 开发工具 Quartus/ModelSim 20.1.1 安装指南

Intel FPGA 开发工具 Quartus/ModelSim 20.1.1 安装指南

【下载地址】IntelFPGA开发工具QuartusModelSim20.1.1安装指南分享 Intel FPGA 开发工具 Quartus/ModelSim 20.1.1 安装指南本资源文件提供了Intel FPGA开发工具Quartus和ModelSim 20.1.1版本的安装包及相关文件 【下载地址】IntelFPGA开发工具QuartusModelSim20.1.1安装指南分享 项目地址: https://gitcode.com/Resource-Bundle-Collection/e1f2a

本资源文件提供了Intel FPGA开发工具Quartus和ModelSim 20.1.1版本的安装包及相关文件。通过本指南,您可以轻松完成这些工具的安装和配置,以便开始您的FPGA开发工作。

安装步骤

  1. 下载安装包

    • 从提供的资源文件中下载Quartus和ModelSim的安装包。
    • 确保您下载了所有必要的文件,包括主程序、ModelSim和FPGA器件库。
  2. 安装主程序

    • 双击主程序的安装包,开始安装过程。
    • 安装过程中,系统会自动加载其他必要的文件。
  3. 配置ModelSim路径

    • 安装完成后,打开Quartus。
    • Tools - Options - EDA Tools Options中,填入ModelSim的安装路径。
    • 默认路径为C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem
  4. 仿真设置

    • 在仿真时,确保ModelSim路径正确配置。
    • 如果遇到路径问题,请参考安装指南中的详细步骤进行调整。

其他注意事项

  • 外部文本编辑器

    • 如果您使用VSCode等外部文本编辑器,请确保路径设置正确。
    • 路径示例:"C:\Users\vid\AppData\Local\Programs\Microsoft VS Code\Code.exe" -r -g %f:%l
  • 处理器核心设置

    • 在安装过程中,可能会提示未使用全部处理器核心。
    • 可以通过在软件安装目录的assignment_defaults.qdf文件中添加命令set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL来解决。

参考资料

  • 更多详细的安装步骤和使用教程,请参考提供的优快云博客文章。

通过本指南,您可以顺利完成Intel FPGA开发工具Quartus和ModelSim 20.1.1的安装,并开始您的FPGA开发项目。

【下载地址】IntelFPGA开发工具QuartusModelSim20.1.1安装指南分享 Intel FPGA 开发工具 Quartus/ModelSim 20.1.1 安装指南本资源文件提供了Intel FPGA开发工具Quartus和ModelSim 20.1.1版本的安装包及相关文件 【下载地址】IntelFPGA开发工具QuartusModelSim20.1.1安装指南分享 项目地址: https://gitcode.com/Resource-Bundle-Collection/e1f2a

创作声明:本文部分内容由AI辅助生成(AIGC),仅供参考

Using: C:\intelFPGA\20.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off alu -c alu --vector_source="C:/Users/18145/Downloads/alu181/alu181/alu1/Waveform2.vwf" --testbench_file="C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/Waveform2.vwf.vht" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue May 20 11:58:19 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off alu -c alu --vector_source=C:/Users/18145/Downloads/alu181/alu181/alu1/Waveform2.vwf --testbench_file=C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/Waveform2.vwf.vht Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/" alu -c alu Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue May 20 11:58:21 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/ alu -c alu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file alu.vho in folder "C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4641 megabytes Info: Processing ended: Tue May 20 11:58:22 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** C:/Users/18145/Downloads/alu181/alu181/alu1/simulation/qsim/alu.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do alu.do ** Error: vsim: CreateProcess error: 2 Error.
最新发布
05-21
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