dm365 linux2.6.32内核实现656传输驱动lcd

最新推荐文章于 2025-08-13 23:56:02 发布

gejunxiao1

最新推荐文章于 2025-08-13 23:56:02 发布

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本文链接：https://blog.youkuaiyun.com/gejunxiao1/article/details/6923956

本文介绍了在DAVINCI平台上为视频编码器设置PAL显示模式的具体实现方法。针对不同型号如DM355、DM365进行了详细的寄存器配置说明，并特别注意了在DM365上设置OSD时的参数调整。

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/*
 * setting PAL mode
 */
static void davinci_enc_set_pal(struct vid_enc_mode_info *mode_info)
{

	enableDigitalOutput(0);

	if (cpu_is_davinci_dm355()) {
		dispc_reg_out(VENC_CLKCTL, 0x1);
		dispc_reg_out(VENC_VIDCTL, 0);
		/* DM350 Configure VDAC_CONFIG  */
		__raw_writel(0x0E21A6B6, IO_ADDRESS(DM3XX_VDAC_CONFIG));
	} else if (cpu_is_davinci_dm365()) {
		dispc_reg_out(VENC_VMOD,0x1043);//gjx  1:YCC8; 0: ;4:PAL; 3:Composite output enable.Video encoder enable.
		dispc_reg_out(VENC_CLKCTL, 0x11); //gjx enable digital lcd clock;orignal:0x1
		dispc_reg_out(VENC_VIDCTL, 0x6000); //gjx  vclk pin output enable & vclk polarity inverse(6000)
		dispc_reg_out(VENC_YCCCTL, 0x1); //gjx bt656

		/* Set OSD clock and OSD Sync Adavance registers */
		dispc_reg_out(VENC_OSDCLK0, 1); //gjx 
		dispc_reg_out(VENC_OSDCLK1, 2); //gjx
		dispc_reg_out(VENC_VDPRO, 0x20);//XJX
		__raw_writel(0x081141CF, IO_ADDRESS(DM3XX_VDAC_CONFIG));
	} else {
		/* to set VENC CLK DIV to 1 - final clock is 54 MHz */
		dispc_reg_merge(VENC_VIDCTL, 0, 1 << 1);
		/* Set REC656 Mode */
		dispc_reg_out(VENC_YCCCTL, 0x1);
	}

	dispc_reg_merge(VENC_SYNCCTL, 1 << VENC_SYNCCTL_OVD_SHIFT,
			VENC_SYNCCTL_OVD);

	
	osd_write_left_margin(mode_info->left_margin);
	/* PAL display shows shakiness in the OSD0 when
	 * this is set to upper margin. Need to bump it
	 * by 2 in the case of DM365
	 */

	if (cpu_is_davinci_dm365())
		osd_write_upper_margin(mode_info->upper_margin + 2);
	else
		osd_write_upper_margin(mode_info->upper_margin);

	dispc_reg_merge(VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
	dispc_reg_out(VENC_DACTST, 0x0);
}