<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[followless的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/followless</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; followless]]></copyright><item><title><![CDATA[linux server中搭建questasim 10.6c & ise14.7]]></title><link>https://blog.youkuaiyun.com/followless/article/details/132763226</link><guid>https://blog.youkuaiyun.com/followless/article/details/132763226</guid><author>followless</author><pubDate>Wed, 06 May 2026 21:29:56 +0800</pubDate><description><![CDATA[DS\ISE\bin\nt64\compxlibgui （花了好些时间）2：在linux下找到ise的目录，Xilinx\14.7\。]]></description><category></category></item><item><title><![CDATA[vitis2025.2 microblaze gpio例子]]></title><link>https://blog.youkuaiyun.com/followless/article/details/160833282</link><guid>https://blog.youkuaiyun.com/followless/article/details/160833282</guid><author>followless</author><pubDate>Wed, 06 May 2026 21:29:15 +0800</pubDate><description><![CDATA[最近需要看下microblaze的东西，vitis2025.2变化比较大，就参考下米联客和正点原子microblaze例子，但是他们使用的仍然是sdk或vitis2019版本，和vitis2025.2区别很大， 最常见的是例子找不到了，函数也有些变化。查找了下，当新建platform后，点击Settings,找到drivers 右拉，会出现examples。]]></description><category></category></item><item><title><![CDATA[vivado 自定义IP封装几个问题]]></title><link>https://blog.youkuaiyun.com/followless/article/details/149938072</link><guid>https://blog.youkuaiyun.com/followless/article/details/149938072</guid><author>followless</author><pubDate>Tue, 05 Aug 2025 15:18:15 +0800</pubDate><description><![CDATA[4：容易出问题是几个相同类信号合并一个大的bus。1：首先创建空工程-->加入需要封装文件。2：点击Creat。]]></description><category></category></item><item><title><![CDATA[vivado添加自己ip路径]]></title><link>https://blog.youkuaiyun.com/followless/article/details/149858199</link><guid>https://blog.youkuaiyun.com/followless/article/details/149858199</guid><author>followless</author><pubDate>Sat, 02 Aug 2025 12:58:16 +0800</pubDate><description><![CDATA[创建自己IP后，在vivado添加自己IP路径如下：]]></description><category></category></item><item><title><![CDATA[基础理论学习参考]]></title><link>https://blog.youkuaiyun.com/followless/article/details/147362817</link><guid>https://blog.youkuaiyun.com/followless/article/details/147362817</guid><author>followless</author><pubDate>Sun, 20 Apr 2025 11:16:56 +0800</pubDate><description><![CDATA[基础理论学习参考1： 数电教材、ppt网课bili2：微机原理与接口网课。]]></description><category></category></item><item><title><![CDATA[vscode打开新文件夹后怎么可以不关闭旧文件夹]]></title><link>https://blog.youkuaiyun.com/followless/article/details/146206214</link><guid>https://blog.youkuaiyun.com/followless/article/details/146206214</guid><author>followless</author><pubDate>Wed, 12 Mar 2025 15:19:38 +0800</pubDate><description><![CDATA[vscode小技巧]]></description><category></category></item><item><title><![CDATA[解决ise 下载WARNING:iMPACT:923 - Can not find cable, check cable setup !]]></title><link>https://blog.youkuaiyun.com/followless/article/details/146157838</link><guid>https://blog.youkuaiyun.com/followless/article/details/146157838</guid><author>followless</author><pubDate>Mon, 10 Mar 2025 16:39:05 +0800</pubDate><description><![CDATA[1、右键"此电脑"，点击"管理"，打开"设备管理器"，插上Xilinx下载器后，在"Programming cable"目录下右键选择"Xilinx USB Cable/Xilinx embedded Plattform USB Firmware loader"，选择"卸载设备"，同时勾选"删除此设备的驱动程序软件"。2、拔出Xilinx下载器，在"Jungo"目录下右键选择"WinDriver",选择"卸载设备"，同时勾选"删除此设备的驱动程序软件"。因为虚拟机内安装有vivado和ise。]]></description><category></category></item><item><title><![CDATA[vivado 修改IPxxx.xci文件避免 .gen文件夹位置紊乱]]></title><link>https://blog.youkuaiyun.com/followless/article/details/144129364</link><guid>https://blog.youkuaiyun.com/followless/article/details/144129364</guid><author>followless</author><pubDate>Fri, 29 Nov 2024 10:19:27 +0800</pubDate><description><![CDATA[版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。vivado在2020版本之后所有的IP默认会放在.gen文件夹内，方便版本管理，但是当我们希望将IP放在其他地方单独管理的时候就有些不方便。原文链接：https://blog.youkuaiyun.com/qq_14843999/article/details/128535076。2.在vivado工程中将IP删掉，只删掉过程文件，不删除.xci文件。3.在vivado工程中重新将xci文件添加进来并生成IP。]]></description><category></category></item><item><title><![CDATA[bug - while parsing file included at]]></title><link>https://blog.youkuaiyun.com/followless/article/details/140318536</link><guid>https://blog.youkuaiyun.com/followless/article/details/140318536</guid><author>followless</author><pubDate>Wed, 10 Jul 2024 11:22:29 +0800</pubDate><description><![CDATA[找到这个对应文件tb_top.sv的对应行，发现是一个 `include "inc_tb_tests_xxx.sv"注意：所有要编译文件放在同一个文件夹中，且编译时在该文件夹中进行编译；- 在被include的文件首尾加入。问题点：头文件，重复定义，那么。]]></description><category></category></item><item><title><![CDATA[adobe pdf设置默认打开是滚动而不是单页视图]]></title><link>https://blog.youkuaiyun.com/followless/article/details/140169171</link><guid>https://blog.youkuaiyun.com/followless/article/details/140169171</guid><author>followless</author><pubDate>Thu, 04 Jul 2024 08:48:15 +0800</pubDate><description><![CDATA[每次打开pdf，总是默认单页视图，修改滚动后，下次打开又 一样，有时候比较烦。上班公司用adobe pdf，自己还不能安装其它软件。如下修改，下次打开就是默认滚动了。后面打开编辑->首选项，]]></description><category></category></item><item><title><![CDATA[怎么更改vivado生成log和jou的目录]]></title><link>https://blog.youkuaiyun.com/followless/article/details/133217989</link><guid>https://blog.youkuaiyun.com/followless/article/details/133217989</guid><author>followless</author><pubDate>Sat, 23 Sep 2023 21:08:04 +0800</pubDate><description><![CDATA[有一次不知怎么的改为默认路径D，但是后面就一直在d盘生成log和jou文件，今天发现修改快捷方式属性可以修改回来。]]></description><category></category></item><item><title><![CDATA[vivado本地的工程管理 - tcl保存工程和重建工程，为git提交做准备]]></title><link>https://blog.youkuaiyun.com/followless/article/details/133217300</link><guid>https://blog.youkuaiyun.com/followless/article/details/133217300</guid><author>followless</author><pubDate>Sat, 23 Sep 2023 20:52:49 +0800</pubDate><description><![CDATA[其中，vivado工程在01，源文件hdl，xdc在02，生成的tcl在05，modelsim用的tcl也在scripts。打开时候进入当时的prj的目录,，例如 cd {D:\Project_FPGA\Isp_test_k7\01_Prj}此方法，简单方便，准确。用vivado生成，不用自己每次照着add或inport，有时候出点怪问题，还很难解决。现在vivado到了2022.2后，很大，提交和保持很费空间。宝贵的服务器资源很浪费。（不同的分支在其它地方讲，此处不提）1: 约定本地建立如下文件夹目录。]]></description><category></category></item><item><title><![CDATA[Xilinx ISE14.7左侧怎么恢复以前的布局]]></title><link>https://blog.youkuaiyun.com/followless/article/details/133178006</link><guid>https://blog.youkuaiyun.com/followless/article/details/133178006</guid><author>followless</author><pubDate>Fri, 22 Sep 2023 17:16:27 +0800</pubDate><description><![CDATA[Xilinx ISE14.7左侧怎么恢复以前的布局]]></description><category></category></item><item><title><![CDATA[ddr3 仿真 &几个报错处理 - Warning - Carriage return (0x0D) is not followed by a newline (0x0A).]]></title><link>https://blog.youkuaiyun.com/followless/article/details/132575239</link><guid>https://blog.youkuaiyun.com/followless/article/details/132575239</guid><author>followless</author><pubDate>Wed, 30 Aug 2023 09:14:58 +0800</pubDate><description><![CDATA[4：修改sim_tb_top.v文件，把自己ddr读写的工程加入，替代原xilinx的example_top。1： 建立axi/非axi工程，右键点击ddr-ip，选择输出xilinx官方仿真工程。3： 将官方仿真模型文件和sim_tb_top.v拷贝走。]]></description><category></category></item><item><title><![CDATA[vivado 在线调试]]></title><link>https://blog.youkuaiyun.com/followless/article/details/132574826</link><guid>https://blog.youkuaiyun.com/followless/article/details/132574826</guid><author>followless</author><pubDate>Wed, 30 Aug 2023 08:40:19 +0800</pubDate><description><![CDATA[（2）需要综合并set up debug： Run Synthesis --> Set up debug -->如果有误，需要选择时钟域 -->采样深度，ok。1：ila 比较方便，而且可以仅仅定义一个probes，但是把宽度加多，随后想看什么信号都{}大括号拼合起来，很方便。（1）在观察的信号前面添加(* MARK_DEBUG="true" *)，；2：markdebug，从ise转来的工程师很喜欢。]]></description><category></category></item><item><title><![CDATA[vivado2020.1 & modelsim 2020.4 联合仿真出错个例]]></title><link>https://blog.youkuaiyun.com/followless/article/details/132491614</link><guid>https://blog.youkuaiyun.com/followless/article/details/132491614</guid><author>followless</author><pubDate>Fri, 25 Aug 2023 11:45:46 +0800</pubDate><description><![CDATA[1： 安装了vivado2020.1 &modelsim 2020.4，设置tools选择仿真工具是modelsim后，可以打开。那么就把独立modelsim仿真的工程文件夹，在xx.sim\sim_1的wordk文件夹和.mpf文件删掉。3：那么尝试修改modelsim.ini，方法就是把生成库里面modelsim.ini相关地方拷贝到modelsim安装目录下的modelsim.ini对应地方（此文件该地方是空的）首先vivado和modelsim是有版本关联的。]]></description><category></category></item><item><title><![CDATA[关于DDR3 IP核使用导入ucf文件，default设置的xilinx 报错处理记录]]></title><link>https://blog.youkuaiyun.com/followless/article/details/132426247</link><guid>https://blog.youkuaiyun.com/followless/article/details/132426247</guid><author>followless</author><pubDate>Tue, 22 Aug 2023 14:14:54 +0800</pubDate><description><![CDATA[ddr3 报错]]></description><category></category></item><item><title><![CDATA[解决 VM虚拟机客户机内核数量是设置的处理器内核数量一半的问题]]></title><link>https://blog.youkuaiyun.com/followless/article/details/126867279</link><guid>https://blog.youkuaiyun.com/followless/article/details/126867279</guid><author>followless</author><pubDate>Thu, 15 Sep 2022 11:05:15 +0800</pubDate><description><![CDATA[解决 VM虚拟机客户机内核数量是设置的处理器内核数量一半的问题]]></description><category></category></item><item><title><![CDATA[Vivado 2018.3 ILA的debug信息保存与读取]]></title><link>https://blog.youkuaiyun.com/followless/article/details/126726510</link><guid>https://blog.youkuaiyun.com/followless/article/details/126726510</guid><author>followless</author><pubDate>Tue, 06 Sep 2022 16:20:58 +0800</pubDate><description><![CDATA[ILA使用]]></description><category></category></item><item><title><![CDATA[4.1.1. VDES终端四层架构模型]]></title><link>https://blog.youkuaiyun.com/followless/article/details/119445733</link><guid>https://blog.youkuaiyun.com/followless/article/details/119445733</guid><author>followless</author><pubDate>Fri, 06 Aug 2021 09:52:41 +0800</pubDate><description><![CDATA[在VDES终端中：

物理层负责VDES原始比特流在物理介质上的传输和接收，对信号进行调制、传输时的滤波/整形、接收时的放大、滤波、时频同步、解调和解码。
	链路层：
根据G1139建议书,VDE通信分为VDE-TER(VHF波段数据交换-岸基通信业务:VHF Data Exchange-Terrestrial)和VDE-SAT(VHF波段数据交换-卫星通信业务:VHF Data ExchangeSatellite)两种业务,这两种业务遵循统一的VDES通信协议架构, 但是在链路层的实现上是两...]]></description><category></category></item></channel></rss>