已知module median_filter_core (
input clk,
input rstn,
input [20:0] base_addr, // ?top??????????
input [63:0] mem_di, // ???????
output reg [20:0] mem_adr, // ??????
output reg [63:0] mem_do, // ???????
output reg mem_csn, // ?????????
output reg [7:0] mem_wen, // ??????????
input start, // ????
output reg done // ??????
);
// --------------------------------------------
// ????
// --------------------------------------------
parameter IMG_WIDTH = 256; // ????????
parameter IMG_HEIGHT = 256; // ????????
parameter PIXEL_BITS = 16; // ????????16?????
// ????????????enum?
parameter IDLE = 3'd0,
READ_ROW1 = 3'd1,
READ_ROW2 = 3'd2,
READ_ROW3 = 3'd3,
SORTING = 3'd4,
WRITE_MEDIAN = 3'd5,
UPDATE_POS = 3'd6,
FINISH = 3'd7;
// --------------------------------------------
// ?????
// --------------------------------------------
reg [2:0] state; // ???
reg [15:0] window_0, window_1, window_2,
window_3, window_4, window_5,
window_6, window_7, window_8; // 3x3????
reg [20:0] x, y; // ????????
reg [20:0] current_addr; // ??????
reg [3:0] read_steps; // ???????
reg [3:0] sort_counter; // ???????
reg [15:0] median_value; // ???????
integer i; // Verilog-2001?????????
// --------------------------------------------
// ????????
// --------------------------------------------
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
state <= IDLE;
done <= 0;
mem_csn <= 1;
mem_wen <= 8'hFF;
x <= 1;
y <= 1;
current_addr <= 0;
read_steps <= 0;
sort_counter <= 0;
// ????????Verilog-2001?????
window_0 <= 0; window_1 <= 0; window_2 <= 0;
window_3 <= 0; window_4 <= 0; window_5 <= 0;
window_6 <= 0; window_7 <= 0; window_8 <= 0;
end
end
// --------------------------------------------
// ????
// --------------------------------------------
always @(posedge clk) begin
if (!rstn) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
done <= 0;
if (start) begin
current_addr <= base_addr + (IMG_WIDTH + 1)*2; // ????(1,1)??
state <= READ_ROW1;
mem_csn <= 0;
mem_adr <= base_addr;
end
end
READ_ROW1: begin
mem_adr <= current_addr - IMG_WIDTH*2 - 2; // (x-1,y-1)
state <= READ_ROW2;
end
READ_ROW2: begin
window_0 <= mem_di[15:0]; // ??????
mem_adr <= current_addr - IMG_WIDTH*2; // (x,y-1)
state <= READ_ROW3;
end
READ_ROW3: begin
window_1 <= mem_di[15:0]; // ??????
window_3 <= mem_di[63:48]; // ??????
mem_adr <= current_addr; // (x,y)????
state <= SORTING;
end
SORTING: begin
// ????????????????
if (window_1 > window_3) begin
median_value <= (window_1 + window_3) / 2;
end else begin
median_value <= (window_3 + window_1) / 2;
end
state <= WRITE_MEDIAN;
end
WRITE_MEDIAN: begin
mem_do <= {4{median_value}}; // 64????
mem_wen <= 8'h00; // ??????
state <= UPDATE_POS;
end
UPDATE_POS: begin
mem_wen <= 8'hFF; // ?????
if (x < IMG_WIDTH-2) begin
x <= x + 1;
current_addr <= current_addr + 2; // ???????2??
end else begin
x <= 1;
if (y < IMG_HEIGHT-2) begin
y <= y + 1;
current_addr <= current_addr + 4; // ???
end else begin
state <= FINISH;
end
end
if (state != FINISH) begin
state <= READ_ROW1;
end
end
FINISH: begin
done <= 1;
state <= IDLE;
end
endcase
end
end
endmodule和module median_filter_core (
input clk,
input rstn,
input [20:0] base_addr, // ?top??????????
input [63:0] mem_di, // ???????
output reg [20:0] mem_adr, // ??????
output reg [63:0] mem_do, // ???????
output reg mem_csn, // ?????????
output reg [7:0] mem_wen, // ??????????
input start, // ????
output reg done // ??????
);
// --------------------------------------------
// ????
// --------------------------------------------
parameter IMG_WIDTH = 256; // ????????
parameter IMG_HEIGHT = 256; // ????????
parameter PIXEL_BITS = 16; // ????????16?????
// ????????????enum?
parameter IDLE = 3'd0,
READ_ROW1 = 3'd1,
READ_ROW2 = 3'd2,
READ_ROW3 = 3'd3,
SORTING = 3'd4,
WRITE_MEDIAN = 3'd5,
UPDATE_POS = 3'd6,
FINISH = 3'd7;
// --------------------------------------------
// ?????
// --------------------------------------------
reg [2:0] state; // ???
reg [15:0] window_0, window_1, window_2,
window_3, window_4, window_5,
window_6, window_7, window_8; // 3x3????
reg [20:0] x, y; // ????????
reg [20:0] current_addr; // ??????
reg [3:0] read_steps; // ???????
reg [3:0] sort_counter; // ???????
reg [15:0] median_value; // ???????
integer i; // Verilog-2001?????????
// --------------------------------------------
// ????????
// --------------------------------------------
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
state <= IDLE;
done <= 0;
mem_csn <= 1;
mem_wen <= 8'hFF;
x <= 1;
y <= 1;
current_addr <= 0;
read_steps <= 0;
sort_counter <= 0;
// ????????Verilog-2001?????
window_0 <= 0; window_1 <= 0; window_2 <= 0;
window_3 <= 0; window_4 <= 0; window_5 <= 0;
window_6 <= 0; window_7 <= 0; window_8 <= 0;
end
end
// --------------------------------------------
// ????
// --------------------------------------------
always @(posedge clk) begin
if (!rstn) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
done <= 0;
if (start) begin
current_addr <= base_addr + (IMG_WIDTH + 1)*2; // ????(1,1)??
state <= READ_ROW1;
mem_csn <= 0;
mem_adr <= base_addr;
end
end
READ_ROW1: begin
mem_adr <= current_addr - IMG_WIDTH*2 - 2; // (x-1,y-1)
state <= READ_ROW2;
end
READ_ROW2: begin
window_0 <= mem_di[15:0]; // ??????
mem_adr <= current_addr - IMG_WIDTH*2; // (x,y-1)
state <= READ_ROW3;
end
READ_ROW3: begin
window_1 <= mem_di[15:0]; // ??????
window_3 <= mem_di[63:48]; // ??????
mem_adr <= current_addr; // (x,y)????
state <= SORTING;
end
SORTING: begin
// ????????????????
if (window_1 > window_3) begin
median_value <= (window_1 + window_3) / 2;
end else begin
median_value <= (window_3 + window_1) / 2;
end
state <= WRITE_MEDIAN;
end
WRITE_MEDIAN: begin
mem_do <= {4{median_value}}; // 64????
mem_wen <= 8'h00; // ??????
state <= UPDATE_POS;
end
UPDATE_POS: begin
mem_wen <= 8'hFF; // ?????
if (x < IMG_WIDTH-2) begin
x <= x + 1;
current_addr <= current_addr + 2; // ???????2??
end else begin
x <= 1;
if (y < IMG_HEIGHT-2) begin
y <= y + 1;
current_addr <= current_addr + 4; // ???
end else begin
state <= FINISH;
end
end
if (state != FINISH) begin
state <= READ_ROW1;
end
end
FINISH: begin
done <= 1;
state <= IDLE;
end
endcase
end
end
endmodule和module median_filter_core (
input clk,
input rstn,
input [20:0] base_addr, // ?top??????????
input [63:0] mem_di, // ???????
output reg [20:0] mem_adr, // ??????
output reg [63:0] mem_do, // ???????
output reg mem_csn, // ?????????
output reg [7:0] mem_wen, // ??????????
input start, // ????
output reg done // ??????
);
// --------------------------------------------
// ????
// --------------------------------------------
parameter IMG_WIDTH = 256; // ????????
parameter IMG_HEIGHT = 256; // ????????
parameter PIXEL_BITS = 16; // ????????16?????
// ????????????enum?
parameter IDLE = 3'd0,
READ_ROW1 = 3'd1,
READ_ROW2 = 3'd2,
READ_ROW3 = 3'd3,
SORTING = 3'd4,
WRITE_MEDIAN = 3'd5,
UPDATE_POS = 3'd6,
FINISH = 3'd7;
// --------------------------------------------
// ?????
// --------------------------------------------
reg [2:0] state; // ???
reg [15:0] window_0, window_1, window_2,
window_3, window_4, window_5,
window_6, window_7, window_8; // 3x3????
reg [20:0] x, y; // ????????
reg [20:0] current_addr; // ??????
reg [3:0] read_steps; // ???????
reg [3:0] sort_counter; // ???????
reg [15:0] median_value; // ???????
integer i; // Verilog-2001?????????
// --------------------------------------------
// ????????
// --------------------------------------------
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
state <= IDLE;
done <= 0;
mem_csn <= 1;
mem_wen <= 8'hFF;
x <= 1;
y <= 1;
current_addr <= 0;
read_steps <= 0;
sort_counter <= 0;
// ????????Verilog-2001?????
window_0 <= 0; window_1 <= 0; window_2 <= 0;
window_3 <= 0; window_4 <= 0; window_5 <= 0;
window_6 <= 0; window_7 <= 0; window_8 <= 0;
end
end
// --------------------------------------------
// ????
// --------------------------------------------
always @(posedge clk) begin
if (!rstn) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
done <= 0;
if (start) begin
current_addr <= base_addr + (IMG_WIDTH + 1)*2; // ????(1,1)??
state <= READ_ROW1;
mem_csn <= 0;
mem_adr <= base_addr;
end
end
READ_ROW1: begin
mem_adr <= current_addr - IMG_WIDTH*2 - 2; // (x-1,y-1)
state <= READ_ROW2;
end
READ_ROW2: begin
window_0 <= mem_di[15:0]; // ??????
mem_adr <= current_addr - IMG_WIDTH*2; // (x,y-1)
state <= READ_ROW3;
end
READ_ROW3: begin
window_1 <= mem_di[15:0]; // ??????
window_3 <= mem_di[63:48]; // ??????
mem_adr <= current_addr; // (x,y)????
state <= SORTING;
end
SORTING: begin
// ????????????????
if (window_1 > window_3) begin
median_value <= (window_1 + window_3) / 2;
end else begin
median_value <= (window_3 + window_1) / 2;
end
state <= WRITE_MEDIAN;
end
WRITE_MEDIAN: begin
mem_do <= {4{median_value}}; // 64????
mem_wen <= 8'h00; // ??????
state <= UPDATE_POS;
end
UPDATE_POS: begin
mem_wen <= 8'hFF; // ?????
if (x < IMG_WIDTH-2) begin
x <= x + 1;
current_addr <= current_addr + 2; // ???????2??
end else begin
x <= 1;
if (y < IMG_HEIGHT-2) begin
y <= y + 1;
current_addr <= current_addr + 4; // ???
end else begin
state <= FINISH;
end
end
if (state != FINISH) begin
state <= READ_ROW1;
end
end
FINISH: begin
done <= 1;
state <= IDLE;
end
endcase
end
end
endmodule完成中值滤波的算法设计
其中滤波的窗口采用3x3大小；
算法测试时，采用目录中的测试图像作为输入，验证算法效果。
注：测试图像包含了两种格式，一种是bmp格式的RGB888，另一为raw格式，仅仅包含灰度信息，每一个像素的灰度信息为16-bit（也就是两个byte）；
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