Unknown verification type [*] in stack map frame

本文介绍如何下载并修改Proguard源码以实现特定的混淆需求,包括修改源码、编译过程及替换jar文件的方法。

1. 下载Ant和Proguard源码

  Ant官网: http://ant.apache.org

  Proguard官网: https://www.guardsquare.com/en/proguard


2. 修改Proguard源码: src/proguard/classfile/ClassConstants.java 
  将ATTR_StackMapTable的值StackMapTable替换为dummy,如下:



3. 编译Proguard源码
 
完成Ant环境的配置后,进入Proguard源码的buildscripts目录下,双击执行build.sh脚本(Windows系统需安装、配置Git):



4.替换proguard.jar

(a)方法一:修改Proguard源码后,编译替换AS/ADT目录下的proguard.jar



(b)方法二:修改Proguard源码后,将编译生成的proguard.jar,放置到AS工程目录下,再配置Gradle

参考:https://www.guardsquare.com/en/proguard/manual/gradle

When using SystemVerilog for digital IC verification, the following types of coverage are commonly used: ### Code Coverage - **Line Coverage**: Measures whether each line of code in the design has been executed. It helps identify dead code that is never reached during simulation. ```systemverilog module example; reg a, b, c; always @(*) begin c = a & b; // Line to be covered end endmodule ``` - **Toggle Coverage**: Checks if signals in the design have changed their values. This is important for ensuring that all possible signal transitions are being exercised. ```systemverilog module toggle_example; reg clk; reg data; always @(posedge clk) begin data <= ~data; // Signal toggling end endmodule ``` - **Branch Coverage**: Determines if all possible branches in conditional statements (e.g., `if-else`, `case` statements) have been taken. ```systemverilog module branch_example; reg [1:0] sel; reg out; always @(*) begin case(sel) 2&#39;b00: out = 1&#39;b0; 2&#39;b01: out = 1&#39;b1; 2&#39;b10: out = 1&#39;b0; 2&#39;b11: out = 1&#39;b1; endcase end endmodule ``` - **Expression Coverage**: Evaluates if all possible combinations of expressions in the code have been computed. ### Functional Coverage - **Scenario Coverage**: Ensures that all defined functional scenarios of the design have been tested. For example, in a memory controller, scenarios could include read, write, burst read, and burst write operations. ```systemverilog covergroup mem_operations; coverpoint mem_cmd { bins read = {READ}; bins write = {WRITE}; bins burst_read = {BURST_READ}; bins burst_write = {BURST_WRITE}; } endgroup ``` - **Data Coverage**: Focuses on the range and combinations of data values used during verification. For instance, in a multiplier, different input data values should be tested. ```systemverilog covergroup multiplier_data; coverpoint a { bins small = {[0:10]}; bins medium = {[11:100]}; bins large = {[101:255]}; } coverpoint b; cross a, b; endgroup ``` ### Assertion Coverage - **Assertion Firing Coverage**: Measures whether assertions in the design have fired (either passed or failed). Assertions are used to check the correctness of the design&#39;s behavior. ```systemverilog module assertion_example; reg clk; reg reset; reg valid; assert property (@(posedge clk) valid |->!reset); cover property (@(posedge clk) valid |->!reset); endmodule ``` ### State Machine Coverage - **State Coverage**: Verifies that all states in a finite state machine (FSM) have been reached. ```systemverilog module fsm_example; reg clk; reg reset; typedef enum {S0, S1, S2} state_type; state_type state; always @(posedge clk or posedge reset) begin if (reset) state <= S0; else case(state) S0: state <= S1; S1: state <= S2; S2: state <= S0; endcase end covergroup fsm_coverage; coverpoint state; endgroup endmodule ``` - **State Transition Coverage**: Checks if all possible state transitions in the FSM have occurred.
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值