<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[dimples_Song的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/dimples_Song</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; dimples_Song]]></copyright><item><title><![CDATA[Xilinx FPGA 使用Microblaze实现串口命令行]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/125837493</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/125837493</guid><author>dimples_Song</author><pubDate>Sun, 17 Jul 2022 23:20:31 +0800</pubDate><description><![CDATA[Xilinx FPGA MicroBlaze实现一个串口命令行]]></description><category></category></item><item><title><![CDATA[vcs+verdi简单的仿真]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/125429945</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/125429945</guid><author>dimples_Song</author><pubDate>Thu, 23 Jun 2022 16:42:53 +0800</pubDate><description><![CDATA[vcs+verdi简单的仿真]]></description><category></category></item><item><title><![CDATA[分享一个ADI开源的数据跨时钟处理模块]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/122923496</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/122923496</guid><author>dimples_Song</author><pubDate>Mon, 14 Feb 2022 14:15:16 +0800</pubDate><description><![CDATA[FPGA设计中数据跨时钟处理]]></description><category></category></item><item><title><![CDATA[Intel FPGA I/O input delay 和output delay约束的例子]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/121446974</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/121446974</guid><author>dimples_Song</author><pubDate>Sat, 20 Nov 2021 22:47:29 +0800</pubDate><description><![CDATA[例子来自《Quartus Prime TimeQuest Timing Analyzer Cookbook》

讲了关于如何约束I/O管脚delay的问题。大致思路是，约束实际的时钟和生成虚拟的时钟，设置硬件delay参数，根据input delay 和output delay的计算公式进行约束。以下为原文。

Input and Output Delays with Virtual Clocks

All input and output delays should reference a virtu..]]></description><category></category></item><item><title><![CDATA[Linux下安装sublime text 3并创建桌面快捷方式]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/106521915</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/106521915</guid><author>dimples_Song</author><pubDate>Wed, 03 Jun 2020 13:22:20 +0800</pubDate><description><![CDATA[Linux下安装sublime text 3并创建桌面快捷方式写在前面sublime text 3 linux安装包下载sublime text 3安装包解压缩添加sublime text 3快捷方式
写在前面
本博客记录了linux下sublime text 3的安装过程，并提供了安装包下载链接。博客所记录的安装过程可能不是非常严谨，笔者只是做个记录以备后续查看，读者在具体操作的时候遇到的问题可以百度其他的教程。
sublime text 3 linux安装包下载
安装包下载链接: sublime tex]]></description><category></category></item><item><title><![CDATA[Quartus中使用SignalTap观察被优化的reg与wire信号]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/106307822</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/106307822</guid><author>dimples_Song</author><pubDate>Sat, 23 May 2020 23:24:52 +0800</pubDate><description><![CDATA[Quartus中使用SignalTap观察被优化的reg与wire信号参考博客我的理解笔者使用的方法不足之处
参考博客
可以先看一下参考博客，讲的还算很详细。https://www.cnblogs.com/oomusou/archive/2008/10/17/signaltap_ii_reg_wire.html
我的理解
参考博客中讲到，为了防止Quartus工具优化我们定义的wire和reg信号，可以在其定义前加约束，例如wire信号如下约束：
(* keep *)wire     a;
或者
wire ]]></description><category></category></item><item><title><![CDATA[一个简单的用户接口转axi lite接口读写BRAM的例子]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/103437648</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/103437648</guid><author>dimples_Song</author><pubDate>Sat, 07 Dec 2019 17:44:33 +0800</pubDate><description><![CDATA[首先借用开源的axi_master模块，首先我用XHDL工具把VHDL转成了Verilog，并将其打包成了IP，名为axi_lite_master_vlog_v1_0。

用户侧handshake接口如下所示，依次表示：写请求，读请求，写完成，读完成，写数据，写地址，读数据，读地址。当然要注意一下接口方向。



axi lite master端接口如下所示：



axi litemaster端...]]></description><category></category></item><item><title><![CDATA[关于FPGA中有符号数表示方法的一些认识]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/103201878</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/103201878</guid><author>dimples_Song</author><pubDate>Fri, 22 Nov 2019 15:52:22 +0800</pubDate><description><![CDATA[有符号数的2进制表示方法是：最高位表示符号位，‘1’表示负数，‘0’表示正数。

   通常负数以补码的形式出现。例如一个4bit数，首先它能够表示的有符号数的范围从-8~7。-8的二进制补码值为4'b1000，-7的二进制补码值为4'b1001...，正数的二进制补码等于它本身，即2的二进制补码值为4'b0010。

   关于有符号数的Verilog写法如下：

...]]></description><category></category></item><item><title><![CDATA[Vivado保存ila波形]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/98521143</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/98521143</guid><author>dimples_Song</author><pubDate>Mon, 05 Aug 2019 21:20:27 +0800</pubDate><description><![CDATA[保存：（write_hw_ila_data + 路径 + [upload_hw_ila_datahw_ila_*]）
write_hw_ila_data F:/work/17_vpss_debug/vid_vpss_vpm/top.srcs/sources_1/ila/fpga_wr_wave [upload_hw_ila_data hw_ila_4]
读取：（read_hw_ila_data ...]]></description><category></category></item><item><title><![CDATA[Vivado与Sublime关联设置]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/88168431</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/88168431</guid><author>dimples_Song</author><pubDate>Tue, 05 Mar 2019 09:46:36 +0800</pubDate><description><![CDATA[1、Tools --&amp;gt;Settings



2、如下图


3、下图位置填入 D:/Program Files/Sublime Text 3/sublime_text.exe [file name]:[line number]    ，前面是路径，后面是固定格式。



4、

与Notepad++等文本编辑器关联也是参照此方法
...]]></description><category></category></item><item><title><![CDATA[[转]BT1120接口及协议]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/86488140</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/86488140</guid><author>dimples_Song</author><pubDate>Tue, 15 Jan 2019 10:18:42 +0800</pubDate><description><![CDATA[原文地址：https://blog.youkuaiyun.com/angelbosj/article/details/49835105

因为项目上用到的是 海思3536的bt1120接口对接 FPGA。项目上用到的是 1920 x 1080@60Hz. 和 3840 x 2160@30hz.

首先讲一下 1920X1080@60HZ,这里走bt1120接口，走的是单边沿。下面 具体讲一下。

      ...]]></description><category></category></item><item><title><![CDATA[Xilinx FPGA配置clocking时钟动态相位输出]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/85341033</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/85341033</guid><author>dimples_Song</author><pubDate>Sat, 29 Dec 2018 16:55:58 +0800</pubDate><description><![CDATA[开发平台基于Vivado2017.3，器件使用的是Kintex7。

先贴个时序图：



如何动态配置clocking输出时钟相位，首先在ip核设置界面，勾选Dynamic Phase Shift，在左侧接口总览里面可以看到多出来4个信号，psclk：用于相移控制信号的驱动时钟，psen：控制相位偏移的使能信号，psincdec：用于相位正负偏移的信号，1表示正向偏移，0表示负向偏移。最后psd...]]></description><category></category></item><item><title><![CDATA[Xilinx MIG DDR3 控制器 Modelsim 仿真]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/84325339</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/84325339</guid><author>dimples_Song</author><pubDate>Wed, 21 Nov 2018 17:06:31 +0800</pubDate><description><![CDATA[        项目上用到图像拼接，输入的视频流要存DDR3，做个DDR3的Modelsim仿真。软件版本用的Vivado2017.3，这个版本生成的Modelsim仿真库好像跟Modelsim10.6版本才兼容。常用的Modelsim仿真库如下四个：secureip，unifast_ver，unimacro_ver，unisims_ver。

       接着我上一篇转载的博客《Modelsi...]]></description><category></category></item><item><title><![CDATA[Modelsim实现对Vivado中的MIG ddr3的仿真]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/84144476</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/84144476</guid><author>dimples_Song</author><pubDate>Fri, 16 Nov 2018 19:12:45 +0800</pubDate><description><![CDATA[原文地址：https://www.cnblogs.com/sepeng/p/6525366.html

    Vivado中的MIG已经集成了modelsim仿真环境，是不是所有IP 都有这个福利呢，不知道哦，没空去验证。

　　第一步：使用vivado中的MIG IP生成一堆东西 ，这个过程自己百度。或者是ug586有step by step 的，so easy。 生成...]]></description><category></category></item><item><title><![CDATA[视频AXI4-Stream to Video Out 调试]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/84073416</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/84073416</guid><author>dimples_Song</author><pubDate>Wed, 14 Nov 2018 20:37:15 +0800</pubDate><description><![CDATA[        本次调试的工作主要是尝试视频标准行场同步信号转AXI4 Stream再转行场数据信号输出。调试的目的在于Xilinx官方好多关于图像处理的Example，其中的视频流格式都是AXI4格式的，故学习一下。

        下图为本测试工程Block设计图。其中Constant0的输出固定值0，Constant1输出固定值1。clk_wiz模块就用了一个locked信号，本来是尝试p...]]></description><category></category></item><item><title><![CDATA[关于video in to axi4-stream]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/83929129</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/83929129</guid><author>dimples_Song</author><pubDate>Sat, 10 Nov 2018 14:13:43 +0800</pubDate><description><![CDATA[PG043 Video In to AXI4-Stream对于video转成AXIS的处理。

关键信号

READY/VALID Handshake

A valid transfer occurs whenever READY, VALID, ACLKEN, and ARESETn are high at the rising edge of ACLK. During valid transf...]]></description><category></category></item><item><title><![CDATA[FPGA调试心得]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/82799303</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/82799303</guid><author>dimples_Song</author><pubDate>Fri, 21 Sep 2018 11:44:48 +0800</pubDate><description><![CDATA[        常规的FPGA调试都是基于单个模块仿真、在线调试，调试通过了再集成到工程里。有时候单个仿真没问题，在线调试也没问题，但是一集成到工程里面就各种莫名其妙各种结果出不来，关于这类事件总结为以下3点：

1、时钟是否安排到位？

2、复位是否安排到位？

3、管脚、时钟等一系列约束是否约束到位？

        基本上以上3点都是致命伤。。。。。。推荐在FPGA设计中，未使用引脚一定要...]]></description><category></category></item><item><title><![CDATA[sublime打开文件乱码的解决方法]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/82117075</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/82117075</guid><author>dimples_Song</author><pubDate>Mon, 27 Aug 2018 18:17:54 +0800</pubDate><description><![CDATA[1、按‘Ctrl’+‘Shift’+‘P’三个键，敲入‘package’跳出如下一些选项，选择‘Package Control：Install Package’。



2、出现如下界面，在空白区域敲‘ConvertToUTF’，点击‘ConvertToUTF8’即可。

由于我sublime已经安装了ConvertToUTF，所以敲进去不显示了。





3、这边的字符也能够正常显示了。


...]]></description><category></category></item><item><title><![CDATA[vivado输出block design 的tcl脚本文件]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/81391615</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/81391615</guid><author>dimples_Song</author><pubDate>Fri, 03 Aug 2018 17:28:13 +0800</pubDate><description><![CDATA[在TCL控制台输入如下命令将BD导出为tcl脚本：

write_bd_tcl E:/dp_tx_ex/bdtcl.tcl，红色框内是tcl脚本导出的路径。

]]></description><category></category></item><item><title><![CDATA[vivado 约束未使用引脚]]></title><link>https://blog.youkuaiyun.com/dimples_Song/article/details/81326747</link><guid>https://blog.youkuaiyun.com/dimples_Song/article/details/81326747</guid><author>dimples_Song</author><pubDate>Wed, 01 Aug 2018 10:52:26 +0800</pubDate><description><![CDATA[set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]

以上语...]]></description><category></category></item></channel></rss>