【转载】关于conv_std_logic_vector 和 conv_integer 这两个函数的使用问题

本文详细介绍了在VHDL中std_logic_arith库的conv_integer函数及其使用,指出该函数不能直接将std_logic_vector转换为整数。同时,解释了std_logic_unsigned和std_logic_signed库中的相关转换函数,并给出了conv_std_logic_vector函数的转换原理和示例。在进行算法设计时,选择正确的库可以避免数据错误。
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源地址:http://blog.sina.com.cn/s/blog_622ef24f0100qlct.html

std_logic_arith
This is the library that defines some types and basic arithmetic operations for representing integers in standard ways. This is a Synopsys extention. The source code is instd_logic_arith.vhd and is freely redistributable.

The unsigned type
The signed type
The arithmetic functions: +, -, *
The comparison functions: <, <=, >, >=, =, /=
The shift functions: shl, shr
The conv_integer function
The conv_unsigned function
The conv_signed function
The conv_std_logic_vector function

-------------------------------------------------------------------------------------------------------------------------------

The conv_integer function
function conv_integer(arg: integer) return integer;
function conv_integer(arg: unsigned) return integer;
function conv_integer(arg: signed) return integer;
function conv_integer(arg: std_ulogic) return small_int;
These functions convert the arg argument to an integer. If the argument contains any undefined elements, a runtime warning is produced and 0 is returned.

The function provided by the std_logic_arith library can't convert a std_logic_vector to an integer because it is impossible to determine if it represents an unsigned or signed value.Functions that do this are included in the std_logic_unsigned and std_logic_signed libraries.

Examples
signal b : std_logic;
signal u1 : unsigned (3 downto 0);
signal s1 : signed (3 downto 0);
signal i1, i2, i3 : integer;
...
u1 <= "1001";
s1 <= "1001";
b <= 'X';
wait for 10 ns;
i1 <= conv_integer(u1); --     9
i2 <= conv_integer(s1); --     -7
i3 <= conv_integer(b);   -- warning produced in simulator

 

以上蓝字说明了一切

1.前一个包含在std_logic_arith.all程序包中

2.后一个在std_logic_unsigned 和std_logic_signed 中都有包含

计算机中的运算都是用2进制补码的,本人总结,在做算法时候,包含std_logic_signed 这个包比较好,这样conv_integer 就把需要转换的数据变成了带符号的整数,然而std_logic_unsigned就把需要转换的数据变成了无符号的整数。

3. conv_std_logic_vector 函数的转换结果是将被转换的数据先转换成2进制补码形式,然后取其低“位长”,作为输出。

如:a<=conv_std_logic_vector(-79,6)----(-79)2c=(10110001)

b<=conv_std_logic_vector(-2,6)-----(-2)2c=(11111110)

c<=conv_std_logic_vector(100,6)-----(100)2c=(01100100)

输出结果:a=110001,b=111110,c=100100

4.本人做了这样的转换conv_std_logic_vector (conv_integer (data),16),data是16范围内的有符号数,但是接口是32位的标准矢量形式(std_logic_vector(31 downto 0)刚开始包括的是std_logic_unsigned 包,发现数据变得面目全非了,想来想去,认为conv_integer (data)的原因,就该了下包,结果就正确了。

转载于:https://www.cnblogs.com/blue-box/articles/4240766.html

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