// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ5424 RDP466 board device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ipq5424-rdp-common.dtsi"
#ifdef __IPQ_MEM_PROFILE_512_MB__
#include "ipq5424-512MB-default-memory.dtsi"
#else
#include "ipq5424-default-memory.dtsi"
#endif
/ {
model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
soc@0 {
tlmm: pinctrl@1000000 {
qup_spi1_default: qup-spi1-default-state {
qup_spi1_clk {
pins = "gpio45";
function = "spi10";
drive-strength = <8>;
bias-disable;
};
qup_spi1_cs {
pins = "gpio46";
function = "spi1_cs";
drive-strength = <8>;
bias-disable;
};
qup_spi1_miso {
pins = "gpio47";
function = "spi10";
drive-strength = <8>;
bias-disable;
};
qup_spi1_mosi {
pins = "gpio48";
function = "spi10";
drive-strength = <8>;
bias-disable;
};
};
audio_pins_pri: audio_pinmux_pri {
mux_1 {
pins = "gpio36";
function = "audio_pri";
drive-strength = <8>;
bias-pull-down;
};
mux_2 {
pins = "gpio37";
function = "audio_pri";
drive-strength = <8>;
bias-pull-down;
};
mux_3 {
pins = "gpio38";
function = "audio_pri";
drive-strength = <8>;
bias-pull-down;
};
mux_4 {
pins = "gpio39";
function = "audio_pri";
drive-strength = <8>;
bias-pull-down;
};
};
};
qupv3: geniqup@1ac0000 {
i2c0: i2c@1a88000 {
pinctrl-0 = <&qup_i2c0_default>;
pinctrl-names = "default";
status = "disabled";
};
spi0: spi@1a90000 {
pinctrl-0 = <&qup_spi0_default>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs128s1", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
spi1: spi@1a94000 {
pinctrl-0 = <&qup_spi1_default>;
pinctrl-names = "default";
status = "disabled";
spidev1: spi@0 {
compatible = "qti,spidev";
reg = <0>;
spi-max-frequency = <9600000>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&gpio_leds_default>;
pinctrl-names = "default";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
};
wsi: wsi {
id = <0>;
num_chip = <3>;
chip_info = <0 2 1 2>,
<1 2 2 0>,
<2 2 0 1>;
status = "okay";
};
mdio@90000 {
/* GPIO40 is for port 1 QCA81XX PHY */
/* GPIO28 is for port 2 QCA81XX PHY */
/* GPIO18 is for QCA8386 switch */
phy-reset-gpio = <
&tlmm 40 GPIO_ACTIVE_LOW
&tlmm 28 GPIO_ACTIVE_LOW
&tlmm 18 GPIO_ACTIVE_LOW
>;
ethernet-phy@4 {
reg = <8>;
compatible ="ethernet-phy-ieee802.3-c45";
};
ethernet-phy@5 {
reg = <12>;
compatible ="ethernet-phy-ieee802.3-c45";
};
switch0@10 {
ports {
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac2>;
dsa-tag-protocol = "qca_8021q";
};
};
};
};
ess-instance {
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
ess-switch@3a000000 {
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0xc>; /* lan port bitmap */
switch_wan_bmp = <0x2>; /* wan port bitmap */
switch_mac_mode = <0xd>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <8>;
ethernet-phy-ieee802.3-c45;
};
port@1 {
port_id = <2>;
phy_address = <12>;
ethernet-phy-ieee802.3-c45;
};
};
};
ess-switch1@1 {
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
link-polling-required = <0>;
fdb_sync = "interrupt";
link-intr-gpio = <&tlmm 41 GPIO_ACTIVE_HIGH>;
};
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
qcom,id = <1>;
reg = <0x3A500000 0x4000>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,phy-mdio-addr = <8>;
qcom,link-poll = <1>;
phy-mode = "usxgmii";
};
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
qcom,id = <2>;
reg = <0x3A504000 0x4000>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,phy-mdio-addr = <12>;
qcom,link-poll = <1>;
phy-mode = "usxgmii";
};
gmac2:dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,mht-dev = <1>;
qcom,is_switch_connected = <1>;
phy-mode = "sgmii";
qcom,ppe-offload-disabled = <1>;
};
/* EDMA host driver configuration for the board */
edma@3ab00000 {
#ifdef __CONFIG_IO_COHERENCY__
dma-coherent;
#endif
qcom,txdesc-ring-start = <4>; /* Tx desc ring start ID */
qcom,txdesc-rings = <16>; /* Total number of Tx desc rings to be provisioned */
qcom,mht-txdesc-rings = <12>; /* Extra Tx desc rings to be provisioned for MHT SW ports */
qcom,txcmpl-ring-start = <4>; /* Tx complete ring start ID */
qcom,txcmpl-rings = <16>; /* Total number of Tx complete rings to be provisioned */
qcom,mht-txcmpl-rings = <12>; /* Extra Tx complete rings to be provisioned for mht sw ports. */
qcom,rxfill-ring-start = <4>; /* Rx fill ring start ID */
qcom,rxfill-rings = <4>; /* Total number of Rx fill rings to be provisioned */
qcom,rxdesc-ring-start = <20>; /* Rx desc ring start ID */
qcom,rxdesc-rings = <4>; /* Total number of Rx desc rings to be provisioned */
qcom,rx-page-mode = <0>; /* Rx fill ring page mode */
qcom,tx-map-priority-level = <1>; /* Tx priority level per port */
qcom,rx-map-priority-level = <1>; /* Rx priority level per core */
qcom,ppeds-num = <4>; /* Number of PPEDS nodes */
/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
qcom,ppeds-map = <1 1 1 1 32 8>, /* PPEDS Node #0 ring and queue map */
<2 2 2 2 40 8>, /* PPEDS Node #1 ring and queue map */
<3 3 3 3 48 8>, /* PPEDS Node #2 ring and queue map */
<0 0 0 0 56 8>; /* PPEDS Node #3 ring and queue map */
qcom,txdesc-map = <4 5 6 7>, /* Port1 per-core Tx ring map */
<8 9 10 11>, /* Port2 per-core Tx ring map */
<12 13 14 15>, /* MHT-Port1 per-core Tx ring map */
<16 17 18 19>, /* MHT-Port2 per-core Tx ring map */
<20 21 22 23>, /* MHT-Port3 per-core Tx ring map */
<24 25 26 27>, /* MHT-Port4 per-core Tx ring map */
<28 29 30 31>; /* Used only for packets from VP */
qcom,txdesc-fc-grp-map = <1 2 3 4 5 6>; /* Per GMAC flow control group map */
qcom,rxfill-map = <4 5 6 7>; /* Per-core Rx fill ring map */
qcom,rxdesc-map = <20 21 22 23>; /* Per-core Rx desc ring map */
qcom,rx-queue-start = <0>; /* Rx queue start */
qcom,rx-ring-queue-map = <0 8 16 24>, /* Priority 0 queues per-core Rx ring map */
<1 9 17 25>, /* Priority 1 queues per-core Rx ring map */
<2 10 18 26>, /* Priority 2 queues per-core Rx ring map */
<3 11 19 27>, /* Priority 3 queues per-core Rx ring map */
<4 12 20 28>, /* Priority 4 queues per-core Rx ring map */
<5 13 21 29>, /* Priority 5 queues per-core Rx ring map */
<6 14 22 30>, /* Priority 6 queues per-core Rx ring map */
<7 15 23 31>; /* Priority 7 queues per-core Rx ring map */
interrupts = <0 286 4>, /* Tx complete ring id #4 IRQ info */
<0 287 4>, /* Tx complete ring id #5 IRQ info */
<0 288 4>, /* Tx complete ring id #6 IRQ info */
<0 289 4>, /* Tx complete ring id #7 IRQ info */
<0 290 4>, /* Tx complete ring id #8 IRQ info */
<0 291 4>, /* Tx complete ring id #9 IRQ info */
<0 292 4>, /* Tx complete ring id #10 IRQ info */
<0 293 4>, /* Tx complete ring id #11 IRQ info */
<0 294 4>, /* Tx complete ring id #12 IRQ info */
<0 295 4>, /* Tx complete ring id #13 IRQ info */
<0 296 4>, /* Tx complete ring id #14 IRQ info */
<0 297 4>, /* Tx complete ring id #15 IRQ info */
<0 298 4>, /* Tx complete ring id #16 IRQ info */
<0 299 4>, /* Tx complete ring id #17 IRQ info */
<0 300 4>, /* Tx complete ring id #18 IRQ info */
<0 301 4>, /* Tx complete ring id #19 IRQ info */
<0 270 4>, /* Rx desc ring id #20 IRQ info */
<0 271 4>, /* Rx desc ring id #21 IRQ info */
<0 272 4>, /* Rx desc ring id #22 IRQ info */
<0 273 4>, /* Rx desc ring id #23 IRQ info */
<0 314 4>, /* Misc error IRQ info */
<0 278 4>, /* RxFill ring id #4 IRQ info */
<0 279 4>, /* RxFill ring id #5 IRQ info */
<0 280 4>, /* RxFill ring id #6 IRQ info */
<0 281 4>, /* RxFill ring id #7 IRQ info */
<0 283 4>, /* PPEDS Node #0(TxComp ring id #1) TxComplete IRQ info */
<0 251 4>, /* PPEDS Node #0(Rx Desc ring id #1) Rx Desc IRQ info */
<0 275 4>, /* PPEDS Node #0(RxFill Desc ring id #1) Rx Fill IRQ info */
<0 284 4>, /* PPEDS Node #1(TxComp ring id #2) TxComplete IRQ info */
<0 252 4>, /* PPEDS Node #1(Rx Desc ring id #2) Rx Desc IRQ info */
<0 276 4>, /* PPEDS Node #1(RxFill Desc ring id #2) Rx Fill IRQ info */
<0 285 4>, /* PPEDS Node #2(TxComp ring id #3) TxComplete IRQ info */
<0 253 4>, /* PPEDS Node #2(Rx Desc ring id #3) Rx Desc IRQ info */
<0 277 4>, /* PPEDS Node #2(RxFill Desc ring id #3) Rx Fill IRQ info */
<0 282 4>, /* PPEDS Node #3(TxComp ring id #0) TxComplete IRQ info */
<0 250 4>, /* PPEDS Node #3(Rx Desc ring id #0) Rx Desc IRQ info */
<0 274 4>, /* PPEDS Node #3(RxFill Desc ring id #0) Rx Fill IRQ info */
<0 302 4>, /* MHT port Tx complete ring id #20 IRQ info */
<0 303 4>, /* MHT port Tx complete ring id #21 IRQ info */
<0 304 4>, /* MHT port Tx complete ring id #22 IRQ info */
<0 305 4>, /* MHT port Tx complete ring id #23 IRQ info */
<0 306 4>, /* MHT port Tx complete ring id #24 IRQ info */
<0 307 4>, /* MHT port Tx complete ring id #25 IRQ info */
<0 308 4>, /* MHT port Tx complete ring id #26 IRQ info */
<0 309 4>, /* MHT port Tx complete ring id #27 IRQ info */
<0 310 4>, /* MHT port Tx complete ring id #28 IRQ info */
<0 311 4>, /* MHT port Tx complete ring id #29 IRQ info */
<0 312 4>, /* MHT port Tx complete ring id #30 IRQ info */
<0 313 4>; /* MHT port Tx complete ring id #31 IRQ info */
};
};
};
&pcm {
pinctrl-0 = <&audio_pins_pri>;
pinctrl-names = "primary";
status = "disabled";
};
&pwm {
pinctrl-0 = <&pwm_default_state>;
pinctrl-names = "default";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
};
&pcie0 {
perst-gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
pcie0_rp {
reg = <0 0 0 0 0>;
};
};
&pcie1 {
perst-gpio = <&tlmm 28 GPIO_ACTIVE_LOW>;
pcie1_rp {
reg = <0 0 0 0 0>;
};
};
&pcie2_phy {
status = "okay";
};
&pcie2 {
status = "okay";
perst-gpio = <&tlmm 31 GPIO_ACTIVE_LOW>;
pcie2_rp {
reg = <0 0 0 0 0>;
qcom,mhi@2 {
reg = <0 0 0 0 0>;
boot-args = <0x2 0x4 0xFF 0x3 0x0 0x0 /* MX Rail, Invalid GPIO, Drive strength 0x3 */
0x5 0x4 0x34 0x3 0x0 0x16 /* CX Rail, GPIO52, Drive strength 0x3, CPR1_fuse 0x0, CPR0_fuse 0x16 */
0x0 0x4 0x0 0x0 0x0 0x0>; /* End of arguments */
memory-region = <&qcn9224_pcie2>, <&mhi_region2>;
qcom,board_id = <0x29>;
qcom,wsi = <&wsi>;
qcom,wsi_index = <1>;
};
};
};
&pcie3_phy {
status = "okay";
};
&pcie3 {
status = "okay";
perst-gpio = <&tlmm 34 GPIO_ACTIVE_LOW>;
pcie3_rp {
reg = <0 0 0 0 0>;
qcom,mhi@3 {
reg = <0 0 0 0 0>;
boot-args = <0x2 0x4 0xFF 0x3 0x0 0x0 /* MX Rail, Invalid GPIO, Drive strength 0x3 */
0x5 0x4 0x34 0x3 0x0 0x16 /* CX Rail, GPIO52, Drive strength 0x3, CPR1_fuse 0x0, CPR0_fuse 0x16 */
0x0 0x4 0x0 0x0 0x0 0x0>; /* End of arguments */
memory-region = <&qcn9224_pcie3>, <&mhi_region3>;
qcom,board_id = <0x28>;
qcom,wsi = <&wsi>;
qcom,wsi_index = <2>;
};
};
};
®_update {
secure-reg = <0x00610a08 0x80>, /* aggr_noc_pcie2 */
<0x00610b08 0x80>; /* aggr_noc_pcie3 */
};
&qusb_phy_1 {
status = "okay";
};
&usb2 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb3 {
status = "okay";
};
&q6v5_wcss {
status = "okay";
};
#if !defined(__RPROC_DISABLE_MPD_SUPPORT__)
&userpd_1 {
status = "okay";
};
#endif
&qcn9224_pcie2 {
status = "okay";
};
&qcn9224_pcie3 {
status = "okay";
};
#if defined(__MHI_BUS_RESERVED_DMA_POOL__)
&mhi_region2 {
status = "okay";
};
&mhi_region3 {
status = "okay";
};
#endif
&tlmm {
gpio_leds_default: gpio-leds-default-state {
pins = "gpio42";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
pcie0_default_state: pcie0-default-state {
perst-n-pins {
pins = "gpio25";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
};
pcie1_default_state: pcie1-default-state {
perst-n-pins {
pins = "gpio28";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
};
pcie2_default_state: pcie2-default-state {
perst-n-pins {
pins = "gpio31";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
};
pcie3_default_state: pcie3-default-state {
perst-n-pins {
pins = "gpio34";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
};
pwm_default_state: pwm-default-state {
pins = "gpio10";
function = "pwm0";
drive-strength = <8>;
};
qspi_default_state: qspi-default-state {
qspi_clock {
pins = "gpio5";
function = "qspi_clk";
drive-strength = <8>;
bias-pull-down;
};
qspi_cs {
pins = "gpio4";
function = "qspi_cs";
drive-strength = <8>;
bias-pull-up;
};
qspi_data {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qspi_data";
drive-strength = <8>;
bias-pull-down;
};
};
qup_spi0_default: qup-spi0-default-state {
qup_spi0_clk {
pins = "gpio6";
function = "spi0_clk";
drive-strength = <8>;
bias-pull-down;
};
qup_spi0_cs {
pins = "gpio7";
function = "spi0_cs";
drive-strength = <8>;
bias-pull-up;
};
qup_spi0_miso {
pins = "gpio8";
function = "spi0_miso";
drive-strength = <8>;
bias-pull-down;
};
qup_spi0_mosi {
pins = "gpio9";
function = "spi0_mosi";
drive-strength = <8>;
bias-pull-down;
};
};
qup_uart1_default: qup-uart1-default-state {
qup_uart1_tx: tx-pins {
pins = "gpio44";
function = "uart1_tx";
drive-strength = <8>;
bias-pull-down;
};
qup_uart1_rx: rx-pins {
pins = "gpio43";
function = "uart1_rx";
drive-strength = <8>;
bias-pull-up;
};
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
qup_i2c0_default: qup-i2c0-default-state {
qup_i2c0_scl {
pins = "gpio14";
function = "i2c0_scl";
drive-strength = <8>;
bias-disable;
};
qup_i2c0_sda {
pins = "gpio15";
function = "i2c0_sda";
drive-strength = <8>;
bias-disable;
};
};
};
&mlo_global_mem0 {
status = "okay";
};
&wifi0 {
qcom,rproc = <&q6v5_wcss>;
qcom,tgt-mem-mode = <0>;
memory-region = <&q6_region>, <&q6_region>;
qcom,wsi = <&wsi>;
qcom,wsi_index = <0>;
qcom,board_id = <0x11>;
hw_link_id = <0 0>;
status = "okay";
};
&wifi3 {
hremote_node = <&qcn9224_pcie2>;
board_id = <0x29>;
hw_link_id = <1 0>;
status = "okay";
};
&wifi4 {
hremote_node = <&qcn9224_pcie3>;
board_id = <0x28>;
hw_link_id = <2 0>;
status = "okay";
};
这是厂商示例的DTS，你就告诉我该把这些代码放这个dts的哪个节点下面怎么改，另外不要sleep功能，另外人家这function不也直接使用了具体名称吗？
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