初学FPGA 实现了一个二进制计时器（记录成长之路）

 我选用的开发板 是黑金的AC7A035，Artix 7。

前期电路综合还是挺顺利的，管脚分配的时候遇到了困难，最后也是顺利解决啦。

TOP文件。

(* keep_hierarchy = "TRUE" *)module count_1(
    input         sys_clk_p,
    input         sys_clk_n,
    input rst,
    input start,
    input stop,
    output [4:0]result
);
   (* dont_touch = "TRUE" *) wire hit;
   (* dont_touch = "TRUE" *) wire clk_1;
   (* dont_touch = "TRUE" *) reg  [4:0]r_result;
   (* dont_touch = "TRUE" *) reg r_start;
   (* dont_touch = "TRUE" *) reg r_stop;
   
    wire clk;
    wire start_1;
    wire stop_1;

    assign stop_1=~stop;//看手册发现按键按下是置零
    assign start_1=~start;
    assign rst_1=~rst;

    IBUFDS sys_clk_ibufgds
    (
         .O (clk),
        .I (sys_clk_p ),
        .IB (sys_clk_n )
    );
    clock_seg clk_seg(
        .clk(clk),
        .rst(rst_1),
        .clk_seg(clk_1)
    );

    always @(posedge start_1 or posedge rst_1) begin
        if(rst_1==1)begin
            r_start <= 1'b0;
        end
        else begin
            r_start <= 1'b1;
        end 
    end

    always @(posedge stop_1 or posedge rst_1) begin
        if(rst_1==1)begin
            r_stop <= 1'b0;
        end
        else begin
            r_stop <= 1'b1;
        end
        
    end

    assign hit = r_start && (~r_stop);


    always @(posedge clk_1 or posedge rst_1) begin
        if(rst_1==1)begin
            r_result <= 5'b00000;
        end
        else begin
            if(r_result == 5'b10000)begin
                r_result <= 5'b00000;
            end
            else begin
                r_result <= r_result + hit;
            end
        end
    end
//看手册点亮灯的规则
    assign result[0] = ~ r_result[0];
    assign result[1] = ~ r_result[1];
    assign result[2] = ~ r_result[2];
    assign result[3] = ~ r_result[3];
    assign result[4] =  r_result[4];
endmodule

处理时钟的模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/12/28 14:41:58
// Design Name: 
// Module Name: clock_seg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module clock_seg#(
    parameter N = 200000000
)(
    input clk,//时钟为200mkhz的时钟
    input rst,
    output clk_seg
    );

    reg r_clk_seg;
    reg [28:0]n;//1011111010111100001000000000

    always @(posedge clk) begin
        if (rst) begin
            n<=28'b0000000000000000000000000000;
        end
        else if (n>=28'b1011111010111100001000000000) begin
            n <= 28'b0000000000000000000000000000;
        end
        else begin
            n <= n + 1'b1;
        end
    end

    always@(n)begin
        if(n == 28'b1011111010111100001000000000)begin
            r_clk_seg <= 1'b1;
        end
        else begin
            r_clk_seg <= 1'b0;
        end
    end

    assign clk_seg = r_clk_seg;

endmodule

最后综合出来的电路