XY2-100的Verilog实现

xy2_100.v

module xy2_100(
	input clk,
	input tx_init, //当产生上升沿时，开始发数据
	input wire [15:0]x_pos,
	input wire [15:0]y_pos,
	input wire [15:0]z_pos,
	
	output clk_2MHz_o,//输出2MHz时钟
	output sync_o,
	output x_ch_o,
	output y_ch_o,
	output z_ch_o,
	output tx_done_o 
);

reg clk_2MHz=1'd1;
reg sync=1'd0;
reg x_ch=1'd0;
reg y_ch=1'd0;
reg z_ch=1'd0;
reg tx_done=1'd0;

assign clk_2MHz_o=clk_2MHz;
assign sync_o=sync;
assign x_ch_o=x_ch;
assign y_ch_o=y_ch;
assign z_ch_o=z_ch;
assign tx_done_o=tx_done;

reg tx_init1=1'd0;
reg tx_init2=1'd0;
wire start_transaction;
assign start_transaction= tx_init1 & (~tx_init2);

reg [5:0]generate_clk_2MHz_cnt=6'd0;
reg [6:0]clk_2MHz_cnt=7'd0;

localparam RefFreq=125000000;
localparam XY2_100_2MHz=2000000;
localparam XY2_100_2MHz_Reverse_Cnt=RefFreq/(2*XY2_100_2MHz);
localparam MaxCnt=2*XY2_100_2MHz_Reverse_Cnt+1; 

always@(posedge clk)
begin
	if(generate_clk_2MHz_cnt==XY2_100_2MHz_Reverse_Cnt)
	begin
		generate_clk_2MHz_cnt<=6'd0;
		clk_2MHz<=~clk_2MHz;
	end
	else
		generate_clk_2MHz_cnt<=generate_clk_2MHz_cnt + 6'd1;
	
	if(clk_2MHz_cnt==MaxCnt)
		clk_2MHz_cnt<=7'd0;
	else
		clk_2MHz_cnt<=clk_2MHz_cnt+7'd1;

	tx_init1<=tx_init;
	tx_init2<=tx_init1;
end

localparam Idle=5'd0;
localparam Wait_First_2MHz_Posedge=5'd1;
localparam C2=5'd2;
localparam C1=5'd3;
localparam C0=5'd4;
localparam D