CPU work loading terms

Process bound:

An excessive amount of processing in the CPU that causes an imbalance between I/O and processing. For example, recalculating a spreadsheet, compiling a program or converting a large graphics file can make a desktop computer process bound.

In a multitasking system, process-bound applications slow down other applications and other users depending on how the operating system slices time (see preemptive multitasking).

CPU bound:

In computer science, CPU bound refers to a condition where the time to complete a computation is determined principally by the speed of the central processor and main memory. This means that the computation is keeping the processor utilization high, and that the processor is not spending much time waiting for interrupts, such as those generated by the arrival of more data from a peripheral device. If a program is CPU bound, it has the potential to run faster provided that a better algorithm can be found to accomplish the computation, or if a faster processor/memory can be used.

The usefulness of the distinction between IO bound and compute bound is based on the empirical observation that many of the uses of computers involve doing a small amount of work to each element of a large set of data, which led to the conclusion that such problems are inherently IO bound. Increasing processor utilization has economic benefits, therefore this observation resulted in a search for techniques to increase processor utilization by minimizing the impact of IO delays. This led to the development of multiprogramming and preemptive scheduling.

I/O bound:

In computer science, I/O bound refers to a condition in which the time it takes to complete a computation is determined principally by the period of time spent waiting for input/output operations to be completed. This is the opposite of a task being compute bound. This circumstance arises when the rate at which data is requested is slower than the rate it is consumed or, in other words, more time is spent requesting data than processing it.

I/O Bound As An Inherent Problem in Computing

The I/O bound state has been identified as a problem in computing almost since its inception. The Von Neumann architecture, which is employed by almost all computing devices ever conceived, is based on a logically-separate central processor Unit which requests data from main memory, processes it and writes back the results. Since data must be moved between the CPU and memory along a bus which has a limited data transfer rate, there exists a condition that is known as the Von Neumann bottleneck. Put simply, this means that the data bandwidth between the CPU and memory tends to limit the overall speed of computation. In terms of the actual technology that makes up a computer, the Von Neumann Bottleneck predicts that it is easier to make the CPU perform calculations faster than it is to supply it with data at the necessary rate for this to be possible.

In recent history, the Von Neumann bottleneck has become more apparent. The design philosophy of modern computers is based upon a physically-separate CPU and main memory. It is possible to make the CPU run at a high data transfer rate because data is moved between locations inside them across tiny distances. The physical separation between CPU and main memory, however, requires a data bus to move data across comparatively long distances of centimetres or more. The problem of making this part of the system operate sufficiently fast to keep up the CPU has been a great challenge to designers.

I/O Bound As A Practical Problem

The I/O bound state is considered undesirable because it means that the CPU must stall its operation while waiting for data to be loaded or unloaded from main memory. With faster computation speed being the primary goal of new computer designs and components such as the CPU and memory being expensive, there is a strong imperative to avoid I/O bound states and eliminating them can yield a more economic improvement in performance than upgrading the CPU or memory.

Determining the location of the ModelSim executable... Using: E:\intelFPGA\18.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source="E:/intelFPGA/WORK/Waveform.vwf" --testbench_file="E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:13 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source=E:/intelFPGA/WORK/Waveform.vwf --testbench_file=E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="E:/intelFPGA/WORK/simulation/qsim/" 1 -c 1 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:14 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=E:/intelFPGA/WORK/simulation/qsim/ 1 -c 1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file 1.vo in folder "E:/intelFPGA/WORK/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4725 megabytes Info: Processing ended: Thu May 22 00:35:15 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** E:/intelFPGA/WORK/simulation/qsim/1.do generated. Completed successfully. **** Running the ModelSim simulation **** E:/intelFPGA/18.1/modelsim_ase/win32aloem/vsim -c -do 1.do Reading E:/intelFPGA/18.1/modelsim_ase/tcl/vsim/pref.tcl # 10.5b # do 1.do # ** Warning: (vlib-34) Library already exists at "work". # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # vsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.1_vlg_vec_tst # Start time: 00:35:15 on May 22,2025 # ** Error: (vsim-3170) Could not find 'work.1_vlg_vec_tst'. # Searched libraries: # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclonev # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_mf # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/220model # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/sgate # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_lnsim # E:/intelFPGA/WORK/simulation/qsim/work # Error loading design Error loading design # End time: 00:35:16 on May 22,2025, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 Error.
05-23
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