OUTREG32 、SETREG32 有什么区别？

最新推荐文章于 2023-11-04 18:05:20 发布
原创 最新推荐文章于 2023-11-04 18:05:20 发布 · 2k 阅读 · 0 ·
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本文详细解析了微软提供的SETREG32与OUTREG32两个宏的区别，通过代码示例说明了SETREG32用于设置寄存器值而不改变其他位，而OUTREG32则会将其他位设为0。

       微软的实现代码如下：

<pre name="code" class="cpp">#define OUTREG32(x, y)      WRITE_REGISTER_ULONG((ULONG*)(x), (ULONG)(y))
#define SETREG32(x, y)      OUTREG32(x, INREG32(x)|(y))

         可以看出，SETREG32，只是设置了y这一位，而不改变其他位，OUTREG32则是y位之外其他位全部设置成0，所以区别就在这里。








    // Note that SETREG32 does read, OR of argument and write, the IRQSTATUS is write '1' to clear,

    // this will clear all interrupt bits, not just the ones in the argument.




                

        

    


  



    



                



	

		

			

				
					
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原标题：【精华推荐】计量经济学十八讲之结果输出命令outreg2 本文转自计量经济学服务中心，由计量经济学服务中心编辑整理。由于outreg2命令为外部命令，所以需要下载安装，使用ssc install outreg2来安装。Linear regression命令outreg2可以帮助你在学术论文中看到的展示类型。注意到这一点很重要，它不是一个Stata命令，它是一个用户编写的过程，您需要通过输入...

			
		

	



                

            
              



	

		

			

				
					
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C语言(*(volatile unsigned CHAR *)addr)理解

				
			

			

				

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嵌入式中C语言操作寄存器看ARM程序时，会看到类似如下的代码：#define SREG     (*(volatile unsigned CHAR *)0x5F)在嵌入式系统编程中，一般要求程序员能够利用C语言访问固定的内存地址。按C语言的语法来看，这个地址应该由指针类型来表示，所以在操作某个内存地址，比如0x5c时，其步骤如下：
将地址强制转换为指针类型 ->（unsigned CHAR * )

			
		

	





	

		

			

				
					
stata结果命令输出之outreg2

				
			

			

				

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stata结果输出；
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几个操作函数的具体定义

				
			

			

				

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//-----------------------------------------------------------------------------
//
//  Header:  common_macros.h
//
//  Provides common macro definitions SOC/BSP code development.
//
//----------

			
		

	





	

		

			

				
					
Stata结果输出：outreg2命令详解

				
			

			

				

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全文阅读：https://www.lianxh.cn/news/d94726e200a8e.html

目录

1. 引言
	2. 描述性分析
	2.1 全部变量一般统计指标
		2.2 部分变量一般统计指标输出
		2.3 全部统计指标输出
		2.4 部分变量部分统计指标输出
		2.5 分组描述性统计量
		2.6 频数
	
	3. 回归结果输出
	3.1 线性回归结果输出
		3.2 面板固定效应回归结果输出
		3.3 逐步增加变量回归合并输出
		3.4 不同模型回归结果合并输出
		3.5 包

			
		

	





	

		

			

				
					
NRF24L01几个函数的分析

				
			

			

				

					棒棒的博客
				

				

					11-19
					
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首先看两个版本关于NRF的宏定义：
开发板：

遥控器：

1，最基本的读写函数，函数的返回值就是读来的数据，形参就是写入的数据
stm32mini开发板例程中：
//SPIx 读写一个字节
//TxData:要写入的字节
//返回值:读取到的字节
u8 SPI1_ReadWriteByte(u8 TxData)
{		
	u8 retry=0;				 	
	while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET) //检查指定的SPI标

			
		

	





	

		

			

				
					
int board_gpio_init(void)
{
    char buffer[BUF_SIZE] = {0};
    U16 pwm_ch = 0;
    U16 val = -1;
    U32 period = 0;
    U32 addr = 0;
    U32 duty = 0;
    U32 u32ModeRIU = 0;
    U32 u32ModeMask = 0;
    U32 u32RegAddr = 0;
    U16 u16RegVal  = 0;
#if defined(WIFI_RESET_GPIO_NUM)
    /********wifi gpio reset init**********/
    memset(buffer, 0, BUF_SIZE);
#ifdef WIFI_RESET_ACTIVE_LEVEL
    printf("wifi gpio reset init. gpio %d level %d\n", WIFI_RESET_GPIO_NUM, WIFI_RESET_ACTIVE_LEVEL);
    if(WIFI_RESET_ACTIVE_LEVEL == 1)
    {
        snprintf(buffer, BUF_SIZE, "gpio clear %d", WIFI_RESET_GPIO_NUM);
        run_command(buffer, 0);
        udelay(100000);
        memset(buffer, 0, BUF_SIZE);
        snprintf(buffer, BUF_SIZE, "gpio set %d", WIFI_RESET_GPIO_NUM);
    }
    else
    {
        snprintf(buffer, BUF_SIZE, "gpio set %d", WIFI_RESET_GPIO_NUM);
        run_command(buffer, 0);
        udelay(100000);
        memset(buffer, 0, BUF_SIZE);
        snprintf(buffer, BUF_SIZE, "gpio clear %d", WIFI_RESET_GPIO_NUM);
    }
#else
    printf("wifi gpio reset init. gpio %d level default high\n", WIFI_RESET_GPIO_NUM);
    snprintf(buffer, BUF_SIZE, "gpio clear %d", WIFI_RESET_GPIO_NUM);
    run_command(buffer, 0);
    udelay(100000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio set %d", WIFI_RESET_GPIO_NUM);
#endif
    run_command(buffer, 0);
#endif
    /********** IR-CUT GPIO INIT **********/
#ifdef CONFIG_MS_GPIO

#if defined(IR_CUT_GPIO_NUM)
    printf("ir-cut gpio init\n");
#ifdef DN_STATUS_GPIO_VALUE_INVERSED
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio set %d", IR_CUT_GPIO_NUM);
    run_command(buffer, 0);
    udelay(150000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio clear %d ", IR_CUT_GPIO_NUM);
    run_command(buffer, 0);
    udelay(150000);
#else
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio clear %d", IR_CUT_GPIO_NUM);
    run_command(buffer, 0);
    udelay(150000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio set %d", IR_CUT_GPIO_NUM);
    run_command(buffer, 0);
    udelay(150000);
#endif
#endif

#if defined(IR_CUT_DOUBLE_GPIO1) && defined(IR_CUT_DOUBLE_GPIO2)
    printf("ir-cut double gpio init\n");
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio clear %d", IR_CUT_DOUBLE_GPIO1);
    run_command(buffer, 0);
    udelay(150000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio set %d", IR_CUT_DOUBLE_GPIO1);
    run_command(buffer, 0);
    udelay(150000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio clear %d", IR_CUT_DOUBLE_GPIO1);
    run_command(buffer, 0);
    udelay(150000);

    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio clear %d", IR_CUT_DOUBLE_GPIO2);
    run_command(buffer, 0);
    udelay(150000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio set %d", IR_CUT_DOUBLE_GPIO2);
    run_command(buffer, 0);
    udelay(150000);
    memset(buffer, 0, BUF_SIZE);
    snprintf(buffer, BUF_SIZE, "gpio clear %d", IR_CUT_DOUBLE_GPIO2);
    run_command(buffer, 0);
    udelay(150000);
#endif

#else

#if defined(IR_CUT_GPIO_NUM) && (IR_CUT_GPIO_NUM==78)
    printf("ir-cut gpio init\n");
    // set pinmux
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE);
    u32ModeMask = REG_TEST_IN_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE);
    u32ModeMask = REG_TEST_OUT_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, REG_SAR_AISEL)) &= (~REG_SAR_CH0_AISEL);
    _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, REG_SAR_AISEL)) &= (~REG_SAR_CH1_AISEL);

#ifdef DN_STATUS_GPIO_VALUE_INVERSED
    // output gpio78 1
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) |= GPIO78_MOUT;
    udelay(150000);
    // output gpio78 0
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) &= (~GPIO78_MOUT);
    udelay(150000);
#else
    // output gpio78 0
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) &= (~GPIO78_MOUT);
    udelay(150000);
    // output gpio78 1
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) |= GPIO78_MOUT;
    udelay(150000);
#endif
#endif

#if defined(IR_CUT_GPIO_NUM) && (IR_CUT_GPIO_NUM==53)
    printf("ir-cut gpio init\n");
#ifdef DN_STATUS_GPIO_VALUE_INVERSED
    // output gpio53 1
    MHal_RIU_REG(GPIO53_ROEN) &= (~GPIO53_MOEN);
    MHal_RIU_REG(GPIO53_ROUT) |= GPIO53_MOUT;
    udelay(150000);
    // output gpio53 0
    MHal_RIU_REG(GPIO53_ROEN) &= (~GPIO53_MOEN);
    MHal_RIU_REG(GPIO53_ROUT) &= (~GPIO53_MOUT);
    udelay(150000);
#else
    // output gpio53 0
    MHal_RIU_REG(GPIO53_ROEN) &= (~GPIO53_MOEN);
    MHal_RIU_REG(GPIO53_ROUT) &= (~GPIO53_MOUT);
    udelay(150000);
    // output gpio53 1
    MHal_RIU_REG(GPIO53_ROEN) &= (~GPIO53_MOEN);
    MHal_RIU_REG(GPIO53_ROUT) |= GPIO53_MOUT;
    udelay(150000);
#endif
#endif

#if (defined(IR_CUT_DOUBLE_GPIO1) && defined(IR_CUT_DOUBLE_GPIO2)) || (defined(IR_CUT_GROUP2_DOUBLE_GPIO1) && defined(IR_CUT_GROUP2_DOUBLE_GPIO2))


#if ((IR_CUT_DOUBLE_GPIO1==78) && (IR_CUT_DOUBLE_GPIO2==79)) || ((IR_CUT_GROUP2_DOUBLE_GPIO1==78) && (IR_CUT_GROUP2_DOUBLE_GPIO2==79))
    printf("ir-cut double gpio init\n");
    // set pinmux
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE);
    u32ModeMask = REG_TEST_IN_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE);
    u32ModeMask = REG_TEST_OUT_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, REG_SAR_AISEL)) &= (~REG_SAR_CH0_AISEL);
    _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, REG_SAR_AISEL)) &= (~REG_SAR_CH1_AISEL);

    // output gpio78 0
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) &= (~GPIO78_MOUT);
    udelay(150000);
    // output gpio78 1
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) |= GPIO78_MOUT;
    udelay(150000);
    // output gpio78 0
    MHal_RIU_REG(GPIO78_ROEN) &= (~GPIO78_MOEN);
    MHal_RIU_REG(GPIO78_ROUT) &= (~GPIO78_MOUT);
    udelay(150000);
    // output gpio79 0
    MHal_RIU_REG(GPIO79_ROEN) &= (~GPIO79_MOEN);
    MHal_RIU_REG(GPIO79_ROUT) &= (~GPIO79_MOUT);
    udelay(150000);
    // output gpio79 1
    MHal_RIU_REG(GPIO79_ROEN) &= (~GPIO79_MOEN);
    MHal_RIU_REG(GPIO79_ROUT) |= GPIO79_MOUT;
    udelay(150000);
    // output gpio79 0
    MHal_RIU_REG(GPIO79_ROEN) &= (~GPIO79_MOEN);
    MHal_RIU_REG(GPIO79_ROUT) &= (~GPIO79_MOUT);
    udelay(150000);
#endif

#if ((IR_CUT_DOUBLE_GPIO1==80) && (IR_CUT_DOUBLE_GPIO2==81)) || ((IR_CUT_GROUP2_DOUBLE_GPIO1==80) && (IR_CUT_GROUP2_DOUBLE_GPIO2==81))
    printf("ir-cut double gpio init  33333333333\n");
    // set pinmux 
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE);
    u32ModeMask = REG_TEST_IN_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE);
    u32ModeMask = REG_TEST_OUT_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, REG_SAR_AISEL)) &= (~REG_SAR_CH0_AISEL);
    _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, REG_SAR_AISEL)) &= (~REG_SAR_CH1_AISEL);

    // output gpio80 0
    MHal_RIU_REG(GPIO80_ROEN) &= (~GPIO80_MOEN);
    MHal_RIU_REG(GPIO80_ROUT) &= (~GPIO80_MOUT);
    udelay(150000);
    // output gpio80 1
    MHal_RIU_REG(GPIO80_ROEN) &= (~GPIO80_MOEN);
    MHal_RIU_REG(GPIO80_ROUT) |= GPIO80_MOUT;
    udelay(150000);
    // output gpio80 0
    MHal_RIU_REG(GPIO80_ROEN) &= (~GPIO80_MOEN);
    MHal_RIU_REG(GPIO80_ROUT) &= (~GPIO80_MOUT);
    udelay(150000);
    // output gpio81 0
    MHal_RIU_REG(GPIO81_ROEN) &= (~GPIO81_MOEN);
    MHal_RIU_REG(GPIO81_ROUT) &= (~GPIO81_MOUT);
    udelay(150000);
    // output gpio81 1
    MHal_RIU_REG(GPIO81_ROEN) &= (~GPIO81_MOEN);
    MHal_RIU_REG(GPIO81_ROUT) |= GPIO81_MOUT;
    udelay(150000);
    // output gpio81 0
    MHal_RIU_REG(GPIO81_ROEN) &= (~GPIO81_MOEN);
    MHal_RIU_REG(GPIO81_ROUT) &= (~GPIO81_MOUT);
    udelay(150000);
#endif


#endif

#endif

#ifdef CONFIG_RESET_MCU_GPIO_NUM
    reset_mcu();
#endif

    /********** IR-WTL SHARE PWM INIT **********/
#if defined(IR_WTL_LED_SHARE_SAME_PWM) && (IR_WTL_LED_PWM_PORT_NUM==52)
    printf("ir-wtl share pwm, set ir gpio init\n");
#if defined(WHITE_LAMP_GPIO_NUM) && (WHITE_LAMP_GPIO_NUM==15)
    // output gpio15 0
    MHal_RIU_REG(GPIO15_ROEN) &= (~GPIO15_MOEN);
    MHal_RIU_REG(GPIO15_ROUT) &= (~GPIO15_MOUT);
    udelay(150000);
#endif
#if defined(IR_LED_GPIO_NUM) && (IR_LED_GPIO_NUM==14)
    // output gpio14 1
    MHal_RIU_REG(GPIO14_ROEN) &= (~GPIO14_MOEN);
    MHal_RIU_REG(GPIO14_ROUT) |= GPIO14_MOUT;
    udelay(150000);
#endif
    printf("ir-wtl led pwm init\n");
    // use pwm0
    pwm_ch = 0;
    // PAD_PWM0   52
    // clear TEST_IN
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x12<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x12<<2), val);
    // clear TEST_OUT
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x12<<2));
    val &= ~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x12<<2), val);
    // clear I2C0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x09<<2));
    val &= ~(0x07);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x09<<2), val);
    // clear I2C1 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x09<<2));
    val &= ~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x009<<2), val);
    // write pwm0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x07<<2));
    val &= ~(0x07);
    val |= 0x01;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x07<<2), val);
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x0E<<9) + (0x28<<2));
    val &= ~(0x03);
    val |= 0x0;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x0E<<9) + (0x28<<2), val);
    // set pwm period:50Khz
    period = 12000000 / 50000;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), (period&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2), ((period>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, period=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), period);
    // set pwm duty:50%
    addr = CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2);
    duty = (INREG16(addr) + ((INREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2))<<16))) * 50 / 100;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), (duty&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x03<<2), ((duty>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, duty=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), duty);
    // enable pwm
    CLRREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (0x7f<<2), 1<<pwm_ch);
#else
    /********** IR-LED PWM INIT **********/
#if defined(IR_LED_GPIO_NUM) && (IR_LED_GPIO_NUM==76)
        memset(buffer, 0, BUF_SIZE);
        snprintf(buffer, BUF_SIZE, "gpio set %d", IR_LED_GPIO_NUM);
        run_command(buffer, 0);
#endif
#if defined(IR_LED_GPIO_NUM) && (IR_LED_GPIO_NUM==14)
#if defined(WHITE_LAMP_GPIO_NUM) && (WHITE_LAMP_GPIO_NUM==15)
    printf("white led gpio init\n");
#if defined(WHITE_LAMP_ACTIVE_LOW) && (WHITE_LAMP_ACTIVE_LOW==1)
    // set output gpio15 to turn off the white lamp
    MHal_RIU_REG(GPIO15_ROEN) &= (~GPIO15_MOEN);
    MHal_RIU_REG(GPIO15_ROUT) |= GPIO15_MOUT;
    udelay(150000);
#endif
#endif
    printf("ir-led pwm init\n");
    // use pwm0
    pwm_ch = 0;
    // clear ej_mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0f<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0f<<2), val);
    // clear spi0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0c<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0c<<2), val);
    // clear fuart mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2), val);
    // clear uart0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2));
    val &= ~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2), val);
    // write pwm0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x07<<2));
    val &= ~(0x03);
    val |= 0x03;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x07<<2), val);
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x0E<<9) + (0x28<<2));
    val &= ~(0x03);
    val |= 0x03;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x0E<<9) + (0x28<<2), val);
    // set pwm period:50Khz
    period = 12000000 / 50000;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), (period&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2), ((period>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, period=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), period);
    // set pwm duty:50%
    addr = CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2);
    duty = (INREG16(addr) + ((INREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2))<<16))) * 50 / 100;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), (duty&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x03<<2), ((duty>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, duty=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), duty);
    // enable pwm
    CLRREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (0x7f<<2), 1<<pwm_ch);
#endif
#if defined(IR_LED_GPIO_NUM) && (IR_LED_GPIO_NUM==53)
    // PAD_PWM1   53
    printf("ir-led pwm init\n");
    // use pwm0
    pwm_ch = 1;
    //clear TEST_IN
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2));
    val &=~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2), val);
    //cclear TEST_OUT
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2));
    val &=~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2), val);
    //clear I2C0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x09<<2));
    val &=~(0x07);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x09<<2), val);
    //clear I2C1 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x09<<2));
    val &=~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x009<<2), val);
    //write pwm1 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x07<<2));
    val &=~(0x38);
    val |= 0x8;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x07<<2), val);
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x0E<<9) + (0x28<<2));
    val &=~(0x0c);
    val |= 0x0;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x0E<<9) + (0x28<<2), val);
    // set pwm period:50Khz
    period = 12000000 / 50000;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), (period&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2), ((period>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, period=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), period);
    // set pwm duty:50%
    addr = CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2);
    duty = (INREG16(addr) + ((INREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2))<<16))) * 50 / 100;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), (duty&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x03<<2), ((duty>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, duty=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), duty);
    // enable pwm
    CLRREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (0x7f<<2), 1<<pwm_ch);
#endif

#if defined(IR_LED_GPIO_NUM) && (IR_LED_GPIO_NUM==16)
    printf("ir-led pwm init\n");
    // use pwm2
    pwm_ch = 2;
    // PAD_FUART_CTS
    //clear EJ_MODE
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0xF<<2));
    val &=~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0xF<<2), val);

    //clear TEST_IN
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2));
    val &=~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2), val);

    //clear TEST_OUT
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2));
    val &=~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2), val);

    //clear SPI0_MODE
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0xC<<2));
    val &=~(0x7);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0xC<<2), val);

    //clear FUART_MODE
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x3<<2));
    val &=~(0x7);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0xC<<2), val);

    //clear FUART1_MODE
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x3<<2));
    val &=~(0x700);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0xC<<2), val);

    //write pwm2 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x07<<2));
    val &=~(0x1C0);
    val |= 0x80;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x07<<2), val);

    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x0E<<9) + (0x28<<2));
    val &=~(0xc0);
    val |= 0x0;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x0E<<9) + (0x28<<2), val);

    //set pwm period/duty
    period = 12000000/5000;

    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x04<<2), (period&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x1a<<9)  + (pwm_ch*0x80) + (0x05<<2), ((period>>16)&0x3));

    printf("reg=0x%08X ,period=0x%x\n",  CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x04<<2), period);

    addr = CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x04<<2);
    duty = (INREG16(addr) + \
                ((INREG16(CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x05<<2))<<16)))*50/100;

    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x02<<2), (duty&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x03<<2), ((duty>>16)&0x3));

    printf("reg=0x%08X ,duty=0x%x\n",  CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (pwm_ch*0x80) + (0x02<<2), duty);

    CLRREG16(CONFIG_RIU_BASE_ADDRESS+(0x1a<<9) + (0x7f<<2), 1<<pwm_ch);
#endif
#endif
    /********** IR-WL PWM INIT **********/
#if defined(WHITE_LAMP_ONLY)
#if (WHITE_LAMP_GPIO_NUM==14)
    printf("ir-wl pwm init use pwm0\n");
    // use pwm0
    pwm_ch = 0;
    // clear ej_mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0f<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0f<<2), val);
    // clear spi0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0c<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x0c<<2), val);
    // clear fuart mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2));
    val &= ~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2), val);
    // clear uart0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2));
    val &= ~(0x30);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x03<<2), val);
    // write pwm0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x07<<2));
    val &= ~(0x03);
    val |= 0x03;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x101E<<9) + (0x07<<2), val);
    val = INREG16(CONFIG_RIU_BASE_ADDRESS + (0x0E<<9) + (0x28<<2));
    val &= ~(0x03);
    val |= 0x03;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x0E<<9) + (0x28<<2), val);
    // set pwm period:50Khz
    period = 12000000 / 50000;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), (period&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2), ((period>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, period=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), period);
    // set pwm duty:10%
    addr = CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2);
    duty = (INREG16(addr) + ((INREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2))<<16))) * 10 / 100;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), (duty&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x03<<2), ((duty>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, duty=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), duty);
    // enable pwm
    CLRREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (0x7f<<2), 1<<pwm_ch);
#else
    printf("ir-wl pwm init use pwm1\n");
    // use pwm0
    pwm_ch = 1;
    //clear ej_mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x0f<<2));
    val &=~(0x03);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x0f<<2), val);
    //clear test0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2));
    val &=~(0x33);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x12<<2), val);
    //clear spi0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x0c<<2));
    val &=~(0x07);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x0c<<2), val);
    //clear fuart mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x03<<2));
    val &=~(0x07);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x03<<2), val);
    //clear uart0 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x03<<2));
    val &=~(0x70);
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x03<<2), val);
    //write pwm1 mode
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x07<<2));
    val &=~(0x18);
    val |= 0x18;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x101E<<9) + (0x07<<2), val);
    val = INREG16(CONFIG_RIU_BASE_ADDRESS+(0x0E<<9) + (0x28<<2));
    val &=~(0x0c);
    val |= 0x0c;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS+(0x0E<<9) + (0x28<<2), val);
    // set pwm period
    period = 12000000 / 50000;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), (period&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2), ((period>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, period=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2), period);
    // set pwm duty
    addr = CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x04<<2);
    duty = (INREG16(addr) + ((INREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x05<<2))<<16))) * 10 / 100;
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), (duty&0xFFFF));
    OUTREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x03<<2), ((duty>>16)&0x3));
    printf("pwm_ch=%d, reg=0x%08X, duty=0x%x\n", pwm_ch, CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (pwm_ch*0x80) + (0x02<<2), duty);
    // enable pwm
    CLRREG16(CONFIG_RIU_BASE_ADDRESS + (0x1A<<9) + (0x7f<<2), 1<<pwm_ch);
#endif	
#endif

    /********** RED/GREEN LED GPIO INIT **********/
#ifdef CONFIG_MS_GPIO

#if defined(LED_RED_GPIO)
    printf("red led gpio init\n");
    memset(buffer, 0, BUF_SIZE);
#if (LED_RED_GPIO_ACTIVE_LOW==1) || defined(LED_GPIO_ACTIVE_LOW)
    snprintf(buffer, BUF_SIZE, "gpio clear %d", LED_RED_GPIO);
#else
    snprintf(buffer, BUF_SIZE, "gpio set %d", LED_RED_GPIO);
#endif
    run_command(buffer, 0);
#endif

#if defined(LED_GREEN_GPIO)
    printf("green led gpio init\n");
    memset(buffer, 0, BUF_SIZE);
#if (LED_GREEN_GPIO_ACTIVE_LOW==1) || defined(LED_GPIO_ACTIVE_LOW)
    snprintf(buffer, BUF_SIZE, "gpio set %d", LED_GREEN_GPIO);
#else
    snprintf(buffer, BUF_SIZE, "gpio clear %d", LED_GREEN_GPIO);
#endif
    run_command(buffer, 0);
#endif

#else

#if defined(LED_RED_GPIO)

#if (LED_RED_GPIO==77)
    printf("red led gpio init\n");
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM5_MODE);
    u32ModeMask = REG_PM_PWM5_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM10_MODE);
    u32ModeMask = REG_PM_PWM10_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE);
    u32ModeMask = REG_PM_VID_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE);
    u32ModeMask = REG_PM_LED_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    MHal_RIU_REG(GPIO77_ROEN) &= (~GPIO77_MOEN);
#if defined(LED_GPIO_ACTIVE_LOW)
    // output gpio77 0
    MHal_RIU_REG(GPIO77_ROUT) &= (~GPIO77_MOUT);
#else
    // output gpio77 1
    MHal_RIU_REG(GPIO77_ROUT) |= GPIO77_MOUT;
#endif
#endif

#if (LED_RED_GPIO==76)
    printf("red led gpio init\n");
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM9_MODE);
    u32ModeMask = REG_PM_PWM9_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE);
    u32ModeMask = REG_PM_VID_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE);
    u32ModeMask = REG_PM_LED_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    MHal_RIU_REG(GPIO76_ROEN) &= (~GPIO76_MOEN);
#if defined(LED_GPIO_ACTIVE_LOW)
    // output gpio76 0
    MHal_RIU_REG(GPIO76_ROUT) &= (~GPIO76_MOUT);
#else
    // output gpio76 1
    MHal_RIU_REG(GPIO76_ROUT) |= GPIO76_MOUT;
#endif
#endif

#endif

#if defined(LED_GREEN_GPIO)

#if (LED_GREEN_GPIO==76)
    printf("green led gpio init\n");
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM9_MODE);
    u32ModeMask = REG_PM_PWM9_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE);
    u32ModeMask = REG_PM_VID_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE);
    u32ModeMask = REG_PM_LED_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    MHal_RIU_REG(GPIO76_ROEN) &= (~GPIO76_MOEN);
#if defined(LED_GPIO_ACTIVE_LOW)
    // output gpio76 1
    MHal_RIU_REG(GPIO76_ROUT) |= GPIO76_MOUT;
#else
    // output gpio76 0
    MHal_RIU_REG(GPIO76_ROUT) &= (~GPIO76_MOUT);
#endif
#endif

#if (LED_GREEN_GPIO==77)
    printf("green led gpio init\n");
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM5_MODE);
    u32ModeMask = REG_PM_PWM5_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM10_MODE);
    u32ModeMask = REG_PM_PWM10_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE);
    u32ModeMask = REG_PM_VID_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    u32ModeRIU = _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE);
    u32ModeMask = REG_PM_LED_MODE_MASK;
    if (_GPIO_R_WORD_MASK(u32ModeRIU, u32ModeMask)) {
        _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
    }
    MHal_RIU_REG(GPIO77_ROEN) &= (~GPIO77_MOEN);
#if defined(LED_GPIO_ACTIVE_LOW)
    // output gpio77 1
    MHal_RIU_REG(GPIO77_ROUT) |= GPIO77_MOUT;
#else
    // output gpio77 0
    MHal_RIU_REG(GPIO77_ROUT) &= (~GPIO77_MOUT);
#endif
#endif

#endif

#if defined(LED_RED_GPIO) && (LED_RED_GPIO==46) && defined(LED_GREEN_GPIO) && (LED_GREEN_GPIO==47)
    u32RegAddr = _RIUA_16BIT(CHIPTOP_BANK, REG_EJ_MODE);
    u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, REG_EJ_MODE_MASK);
    if (u16RegVal) {
        _GPIO_W_WORD_MASK(u32RegAddr, 0, REG_EJ_MODE_MASK);
    }
    u32RegAddr = _RIUA_16BIT(CHIPTOP_BANK, REG_TEST_IN_MODE);
    u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, REG_TEST_IN_MODE_MASK);
    if (u16RegVal) {
        _GPIO_W_WORD_MASK(u32RegAddr, 0, REG_TEST_IN_MODE_MASK);
    }
    u32RegAddr = _RIUA_16BIT(CHIPTOP_BANK, REG_TEST_OUT_MODE);
    u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, REG_TEST_OUT_MODE_MASK);
    if (u16RegVal) {
        _GPIO_W_WORD_MASK(u32RegAddr, 0, REG_TEST_OUT_MODE_MASK);
    }
    u32RegAddr = _RIUA_16BIT(CHIPTOP_BANK, REG_SPI0_MODE);
    u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, REG_SPI0_MODE_MASK);
    if (u16RegVal) {
        _GPIO_W_WORD_MASK(u32RegAddr, 0, REG_SPI0_MODE_MASK);
    }
    u32RegAddr = _RIUA_16BIT(CHIPTOP_BANK, REG_PWM6_MODE);
    u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, REG_PWM6_MODE_MASK);
    if (u16RegVal) {
        _GPIO_W_WORD_MASK(u32RegAddr, 0, REG_PWM6_MODE_MASK);
    }
    u32RegAddr = _RIUA_16BIT(CHIPTOP_BANK, REG_PWM7_MODE);
    u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, REG_PWM7_MODE_MASK);
    if (u16RegVal) {
        _GPIO_W_WORD_MASK(u32RegAddr, 0, REG_PWM7_MODE_MASK);
    }
#if defined(LED_GPIO_ACTIVE_LOW)
    printf("red led gpio init\n");
    MHal_RIU_REG(GPIO46_ROEN) &= (~GPIO46_MOEN);
    // output gpio46 0
    MHal_RIU_REG(GPIO46_ROUT) &= (~GPIO46_MOUT);
    printf("green led gpio init\n");
    MHal_RIU_REG(GPIO47_ROEN) &= (~GPIO47_MOEN);
    // output gpio47 1
    MHal_RIU_REG(GPIO47_ROUT) |= GPIO47_MOUT;
#else
    printf("red led gpio init\n");
    MHal_RIU_REG(GPIO46_ROEN) &= (~GPIO46_MOEN);
    // output gpio46 1
    MHal_RIU_REG(GPIO46_ROUT) |= GPIO46_MOUT;
    printf("green led gpio init\n");
    MHal_RIU_REG(GPIO47_ROEN) &= (~GPIO47_MOEN);
    // output gpio47 0
    MHal_RIU_REG(GPIO47_ROUT) &= (~GPIO47_MOUT);
#endif
#endif
    printf("led gpio init\n");
#if defined(LED_RED_GPIO) && defined(LED_GREEN_GPIO) && defined(LED_RED_GPIO_ACTIVE_LOW) && defined(LED_GREEN_GPIO_ACTIVE_LOW)
#if (LED_RED_GPIO == 44)
	printf("red led gpio init\n");
	memset(buffer, 0, BUF_SIZE);
#if (LED_RED_GPIO_ACTIVE_LOW==1) || defined(LED_GPIO_ACTIVE_LOW)
	snprintf(buffer, BUF_SIZE, "gpio clear %d", LED_RED_GPIO);
#else
	snprintf(buffer, BUF_SIZE, "gpio set %d", LED_RED_GPIO);
#endif
	run_command(buffer, 0);
#if 0
    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE);
    u32ModeMask = REG_EJ_MODE_MASK;
    _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);

    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_ALLPAD_IN_MODE);
    u32ModeMask = REG_ALLPAD_IN_MODE_MASK;
    _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);

    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE);
    u32ModeMask = REG_TEST_IN_MODE_MASK;
    _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);

    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE);
    u32ModeMask = REG_TEST_OUT_MODE_MASK;
    _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);

    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE);
    u32ModeMask = REG_SPI0_MODE_MASK;
    _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);

    u32ModeRIU = _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE);
    u32ModeMask = REG_PWM4_MODE_MASK;
    _GPIO_W_WORD_MASK(u32ModeRIU, 0, u32ModeMask);
#endif
#else
    MHal_GPIO_Pad_EN(GPIO_ROEN(LED_RED_GPIO),GPIO_MOEN(LED_RED_GPIO));
    MHal_GPIO_Pad_EN(GPIO_ROEN(LED_GREEN_GPIO),GPIO_MOEN(LED_GREEN_GPIO));
#if (LED_RED_GPIO_ACTIVE_LOW == 1 && LED_GREEN_GPIO_ACTIVE_LOW == 1)
// output RED 0/GREEN 1
    MHal_GPIO_OutLOW(GPIO_ROUT(LED_RED_GPIO),GPIO_MOUT(LED_RED_GPIO));
    MHal_GPIO_OutHigh(GPIO_ROUT(LED_GREEN_GPIO),GPIO_MOUT(LED_GREEN_GPIO));
    printf("gpio %d out %d,gpio %d out %d\n",LED_RED_GPIO,0,LED_GREEN_GPIO,1);
#endif
#if (LED_RED_GPIO_ACTIVE_LOW == 0 && LED_GREEN_GPIO_ACTIVE_LOW == 1)
// output RED 1/GREEN 1
    MHal_GPIO_OutHigh(GPIO_ROUT(LED_RED_GPIO),GPIO_MOUT(LED_RED_GPIO));
    MHal_GPIO_OutHigh(GPIO_ROUT(LED_GREEN_GPIO),GPIO_MOUT(LED_GREEN_GPIO));
    printf("gpio %d out %d,gpio %d out %d\n",LED_RED_GPIO,1,LED_GREEN_GPIO,1);
#endif
#if (LED_RED_GPIO_ACTIVE_LOW == 1 && LED_GREEN_GPIO_ACTIVE_LOW == 0)
// output RED 0/GREEN 0
    MHal_GPIO_OutLOW(GPIO_ROUT(LED_RED_GPIO),GPIO_MOUT(LED_RED_GPIO));
    MHal_GPIO_OutLOW(GPIO_ROUT(LED_GREEN_GPIO),GPIO_MOUT(LED_GREEN_GPIO));
    printf("gpio %d out %d,gpio %d out %d\n",LED_RED_GPIO,0,LED_GREEN_GPIO,0);
#endif
#if (LED_RED_GPIO_ACTIVE_LOW == 0 && LED_GREEN_GPIO_ACTIVE_LOW == 0)
// output RED 1/GREEN 0
    MHal_GPIO_OutHigh(GPIO_ROUT(LED_RED_GPIO),GPIO_MOUT(LED_RED_GPIO));
    MHal_GPIO_OutLOW(GPIO_ROUT(LED_GREEN_GPIO),GPIO_MOUT(LED_GREEN_GPIO));
    printf("gpio %d out %d,gpio %d out %d\n",LED_RED_GPIO,1,LED_GREEN_GPIO,0);
#endif
#endif
#endif
#endif

#ifdef UPGRADE_LED_GPIO_NUM
    MDrv_GPIO_Pad_Set(UPGRADE_LED_GPIO_NUM);
#endif

    U16 wtd_rst_status;
    wtd_rst_status = INREG16(GET_REG_ADDR(REG_ADDR_BASE_WDT, WDT_RST_RSTLEN));
    printf("wtd rst status: 0x%04X\n", (unsigned int)wtd_rst_status);

    return 0;
}

				
			

			

				

					09-17
				

			

		

		

			
				
好的，我需要分析用户提供的这段C代码，并给出详细的解释。...3. `MHal_RIU_REG` 宏的实现原理是什么？ 4. 如何通过 U-Boot 命令行测试 WiFi 复位功能？ 5. 如果 LED 极性配置错误，如何快速修正？

			
		

	





	

		

			

				
					
stata运行ssc/outreg2闪退

				
			

			

				

					05-13
				

			

		

		

			
				
这时候可以尝试更改Stata的外部命令存储路径，比如使用`sysdir set PERSONAL`命令将路径指向其他有足够空间的磁盘。  另外，用户提到安装时提示“cannot be written to the dictionary”，这可能涉及权限问题。以...

			
		

	





	

		

			

				
					
#define UART_FCR_TRIGGER_TX_L0  0x00    /* Trigger Write when emtpy */
#define UART_FCR_TRIGGER_TX_L1  0x10    /* Trigger Write when 2 characters */
#define UART_FCR_TRIGGER_TX_L2  0x20    /* Trigger Write when 1/4 full */
#define UART_FCR_TRIGGER_TX_L3  0x30    /* Trigger Write when 1/2 full */
#define UART_FCR_TRIGGER_RX_L0  0x00    /* Trigger Read when there is 1 char*/
#define UART_FCR_TRIGGER_RX_L1  0x40    /* Trigger Read when 1/4 full */
#define UART_FCR_TRIGGER_RX_L2  0x80    /* Trigger Read when 1/2 full */
#define UART_FCR_TRIGGER_RX_L3  0xC0    /* Trigger Read when 2 less then full  */OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_TRIGGER_TX_L1 | UART_FCR_TRIGGER_RX_L0);其中SBUS串口这里需要怎么设置才不会出现 726ms 无数据输出 和 连续300ms粘包 的问题

					
最新发布

				
			

			

				

					11-30
				

			

		

		

			
				
OUTREG8(REG_IIR_FCR(p),   UART_FCR_FIFO_ENABLE |   UART_FCR_TRIGGER_TX_L1 | // TX FIFO 少于 2 字节时触发中断（但无效）  UART_FCR_TRIGGER_RX_L0); // RX 收到 1 字节就触发中断 ```  这个配置对 **接收灵敏...

			
		

	





	

		

			

				
					
C中一些常用小结

				
			

			

				

					私房菜
				

				

					06-10
					
					1870
					
				

			

		

		

			
				
1. const1. const它限定一个变量不允许被改变。使用const在一定程度上可以提高程序的安全性和可靠性。// a 代表一个常整型数// a 代表一个常整型数// a 代表一个指向常整型数的指针，即a的值是可变的，但是*a是不能变的，函数的一些形参经常会用到// a 代表一个常指针，即a的值是不可变的，但是*a是可变的// a代表的是一个指向常整型数的常指针1）const + 类型说明const修饰的是类型，想让类型为常量，也就是这个类型的值为常量。例如const int *a。

			
		

	





	

		

			

				
					
LCD 驱动过程详解

					
热门推荐

				
			

			

				

					sunweizhong1024的专栏
				

				

					12-28
					
					2万+
					
				

			

		

		

			
				
MTK 平台LCD 驱动的整个过程的讲解



<!--
p
	{margin-bottom:0.21cm}
-->

MTK_LCD_Driver
代码的路是在/mediatek/source/kernel/driver/vedio/mtkfb.c
module_init(mtkfb_init);模块初始化函数
int__init mtkfb_init(void)
{

			
		

	





	

		

			

				
					
am3352 wince gt ft触摸屏驱动

				
			

			

				

					SVS4414的专栏
				

				

					06-01
					
					2009
					
				

			

		

		

			
				
gt910
/*
 * am335x_adc_touch.cpp
 *
 *  Created on: 2013-3-1
 *      Author: STEVEN
 */


#pragma warning(push)
#pragma warning(disable: 4127 4201)
//---------------------------------------

			
		

	





	

		

			

				
					
再次分析5.0BSP中断

				
			

			

				

					gooogleman#foxmail.com
				

				

					11-10
					
					3189
					
				

			

		

		

			
				
看三星的5.0中断，看的一头雾水，相当郁闷。现在重新理清一下。sontitan牛人也指示过一些。引用楼主 wangxin_801115 的帖子:请问这两个函数KernelIoControl和InterruptInitialize函数的区别是什么呢？？ 个人理解：先用KernelIoControl申请中断号           然后利用InterruptInitialize把 （从Kerne

			
		

	





	

		

			

				
					
matla可以导出回归结果表格吗_Stata结果输出：outreg2命令详解

				
			

			

				

					weixin_42133329的博客
				

				

					12-18
					
					4263
					
				

			

		

		

			
				
? 连享会主页：lianxh.cnNew！lianxh命令发布了：随时搜索 Stata 推文、教程、手册、论坛，安装命令如下：. ssc install lianxh 连享会 · 最受欢迎的课 ?2021 Stata 寒假班⌚ 2021 年 1.25-2.4? 主讲：连玉君 (中山大学)；江艇 (中国人民大学)?课程主页：https://gitee.com/arlionn/PX...

			
		

	





	

		

			

				
					
海思平台SDK原厂bug排雷汇总（不定期更新）

				
			

			

				

					Erwin Chan的博客
				

				

					04-26
					
					1903
					
				

			

		

		

			
				
海思虽然提供了丰富的文档描述和接口支持，但是由于底层代码不可见，很多接口的实现机制描述的不清楚，会导致很多问题难以定位，更难以解决，一般的公司或者学校项目也基本得不到海思原厂的FAE支持。

本文仅据个人观点和经验提供一些常见的bug的解决方案或规避方法。还请各位看官批评指正！

1. 使用uboot烧录文件系统不成功问题


海思除了可以通过串口（串口速率实在太慢了，一般最多用来烧录fastbo...

			
		

	





	

		

			

				
					
Zynq-Linux移植学习笔记之14-RapidIO驱动开发

				
			

			

				

					无知的我
				

				

					05-26
					
					1万+
					
				

			

		

		

			
				
在对zynq进行linux驱动开发时，除了需要针对zynq内ARM自带的控制器适配驱动外，还需要对zynq PL部分的IP核进行驱动开发。对于ARM来说，zynq PL部分的IP核就是一段地址空间，这段地址空间包含了该IP的一系列寄存器，ARM操作该IP核的寄存器也就是操作这段地址空间，而PL部分IP的驱动也就是对IP寄存器的操作。
 
1、  硬件设计
在vivado内进行设计时，Rapi

			
		

	



              




          




        



    





    



      

      

        
      

      





	

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