Clock Domain Crossing (CDC) Verification

最新推荐文章于 2024-10-15 12:29:59 发布

SEU-RC

最新推荐文章于 2024-10-15 12:29:59 发布

阅读量1.3k

点赞数

本文讨论了时钟域穿越(CDC)验证中的关键问题，包括元稳定性、信号同步及数据丢失等现象。当信号从一个时钟域转移到另一个异步时钟域时，可能引发元稳定性问题，导致寄存器状态不稳定；控制信号与数据信号同步不当也会产生问题；此外，从高速时钟域到低速时钟域的数据传递可能导致数据丢失。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

该文转载自:https://www.semiwiki.com/forum/content/375-clock-domain-crossing-verification.html

Paul McLellan

Control signal synchronization

Data signal synchronization

When signals cross from one clock domain to another asynchronous domain, several problems can result:

Metastability. When a signal from the first clock domain is transitioning just as the second clock domain is clocked, there may be an attempt to clock an invalid logic level into a register. The register may take some time to return to a stable state.
Convergence of separately synchronized signals. Since there are times when it is unclear whether a signal will be latched on one clock cycle or the subsequent on, it is possible that two signals changing simultaneously in one clock domain end up a cycle apart in the other domain.
Data loss when a signal crosses from a domain with a faster clock to one with a slower clock, for example. More positive synchronization such as handshaking may be necessary