Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool

Calypto Design Systems宣布已从Mentor Graphics Corporation手中收购了Catapult C Synthesis,此次合并将增强其电子系统级产品,并提供更紧密集成的硬件实现流程。通过结合市场领先的C合成、顺序验证和功率优化产品,Calypto将成为唯一能够提供完全集成流程的公司。

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http://finance.yahoo.com/news/Calypto-Design-Systems-iw-3264204374.html?x=0

SANTA CLARA, CA--(Marketwire -08/26/11)- Calypto Design Systems today announced it has acquired Catapult C Synthesis from Mentor Graphics Corporation (NASDAQ: MENT - News).   The merger of two market-leading electronic system level (ESL) products, Catapult C Synthesis and Calypto SLEC System-HLS verification tool, will create a better integrated ESL hardware realization flow, and enhance the company's partnership with Mentor Graphics, a leader in ESL technology.   Terms of the transaction were not disclosed.

"ESL synthesis offers our design community the next great leap in productivity.   Much like the move to RTL years ago, the move to higher levels of abstraction based on C and SystemC offers the promise of better quality of results in a shorter amount of time.   By combining the market leading products in C synthesis, sequential verification, and power optimization within Calypto, we will be the only company capable of delivering a fully integrated flow, and delivering on that promise of ESL," said Doug Aitelli, Chief Executive Officer of Calypto Design Systems.   "In addition, we remain fully committed to our existing high level synthesis partnerships and to industry-wide interoperability."

"This is a great deal for Calypto," said Gary Smith, Chief Analyst at GSEDA.   "They are clearly one of the companies on the rise in ESL, and this gives them the chance to offer a compelling power-optimized C to RTL flow if they can integrate all the pieces."

ESL methods allow designers to work at a higher level of abstraction, greatly reducing errors and allowing greater optimization of integrated circuits (IC) in key attributes like speed and power.   To adopt ESL methods, designers need to have confidence that tools, as they translate from the higher level of abstraction to lower levels, don't introduce errors.   Typically, designers have used extensive RTL verification to ensure that no errors have been introduced.

SLEC System-HLS uniquely addresses this challenge with C to RTL formal equivalence checking using patented sequential analysis technology to create an easy to use synthesis and verification flow environment.   Designers can perform comprehensive functional verification using SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.   This leads to up to 100x speed up times in RTL verification as it removes the need for significant and time consuming RTL simulation to validate that the RTL matches the C or SystemC source.   Tight integration between Calypto's SLEC System-HLS and Catapult C Synthesis will give designers confidence that the IC they designed in C or SystemC is the IC that is being delivered in RTL.

Additionally, the PowerPro SoC Power Reduction Platform can do RTL level power optimizations.   Added to the Catapult C Synthesis and SLEC System-HLS hardware realization flow, this allows designers to swiftly go from C and System C designs to power-optimized RTL.

"We remain deeply committed to ESL.   We view this transaction as an innovative way to accelerate adoption of ESL methodologies, to strengthen our partnership with Calypto, and as one that complements our continued investment in ESL virtual prototyping environments led by our Vista product," said Brian Derrick, vice president of marketing at Mentor Graphics.   "Calypto's Sequential Logic Equivalency Checker is a critical and unique technology for enabling the adoption of ESL.   Its combination with the market-leading Catapult C Synthesis product and the PowerPro SoC Power Reduction Platform, should give designers the confidence to adopt ESL methods and enjoy the significant benefits that designing at higher levels of abstraction brings."

Current customers of the Mentor Graphics Catapult C Synthesis tool will continue to be supported by Mentor Graphics.   Moving forward, any new customer sales and support will be supplied by Calypto.


PowerPro软件:registered: RTL低功耗,唯一的RTL低功耗解决方案将分析,优化和正式验证的自动RTL生成结合在一起,使设计人员能够快速实现最大,最准确的功耗节省。 概观 无论是为了延长电池寿命,降低电力成本还是遵守法规,电力已成为关键的设计约束和关键的差异化因素。 PowerPro RTL低功耗平台提供了一个完整的解决方案,可在RTL开发周期内准确测量,交互式探索并彻底优化功耗。 使用PowerPro,设计人员可以直接在RTL设计上评估功耗,而不是经历耗时的物理实现步骤。PowerPro的物理感知流程为估计的功率数量提供必要的精度。 在整个开发过程中,电力勘探流程提供了关于浪费电力以及如何减少电力的指导。设计人员还可以执行“假设分析”,交互式评估潜在设计转换对功耗的影响。 最后,作为RTL接近完成时,设计师可以利用优化流程自动生成新的,功率优化RTL,这是使用PowerPro软件的SLEC正式确认:registered:技术,节省了时间/验证时间天。使用获得专利的深度序列分析技术,PowerPro扫描RTL设计,以找到可能关闭芯片冗余部分的最先进逻辑条件。 使用PowerPro,设计人员可以最大限度地降低SoC的功耗。 PowerPro RTL低功耗平台 功率估算 PowerPro提供业界最精确的寄存器传输级(RTL)功耗估算解决方案。PowerPro为FinFET设计开发和优化的全新独特技术使其在精度方面的显着优势成为可能。 引导功率降低 PowerPro的功耗降低功能完全集成在RTL功率估算流程中。在整个RTL设计周期中使用,PowerPro交互式地指导设计人员实现最低功耗的实现。 自动降低功率 低功耗RTL和PowerPro执行的所有优化均由SLEC Pro形式验证引擎全面验证。
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